Students accumulate theoretical insights during the course of their education but it can be much harder for them to obtain high-quality, practical experience related to this knowledge. That is especially true for students in the world of advanced technology, where access to state-of-the-art facilities can be a limited and expensive proposition.
Nabeeh Kandalaft, a doctoral student at the University of Windsor’s Department of Electrical and Computer Engineering, understands this challenge. Kandalaft — together with his thesis advisors Dr. Rashid Rashidzadeh, and Dr. Majid Ahmadi,— has been exploring a better way of testing integrated circuits. When those circuits operate at high frequencies in the gigahertz (GHz) range, degradation of the test signal integrity due to impedance mismatch becomes a major issue.
When the frequency of interaction approaches a few gigahertz, the parasitic effects of physical contact points and the transmission lines between test equipment and the device-under-test become significant enough to degrade the information being transmitted. Currently, wafer-level tests are carried out with a limited set of probes that move automatically over the surface of the wafer, a low-speed test technique that demands great care in order to avoid causing any damage.
Testing is a costly and time-consuming part of chip manufacturing and manufacturers need ways to address this problem of signal integrity degradation.
The University of Windsor research group has developed a way to substantially reduce the size of the contact points between the test equipment and the chip, which limits the unwanted effects. By employing microelectromechanical system (MEMS) techniques, they have designed testing probes that support a contact pad pitch of less than 50 microns. “When the physical separation of the device under test and the test equipment is reduced,” Kandalaft explains, “the effect of transmission line loss and matching impedances decreases.”
Kandalaft, who has been at the University of Windsor since 2008, began this project with computerized simulations of how such a MEMS array would work. In 2010, CMC provided him with the necessary support to spend several weeks at the Laboratoire de Microfabrication (LMF) at École Polytechnique de Montréal. There he mastered sophisticated techniques used in MEMS fabrication, such as Deep Reactive-Ion Etching and Electron Beam Machining.
“The LMF staff were very supportive, helpful, and patient,” he recalls. “It was a priceless, extensive training experience.”
A subsequent CMC grant supported his return to Montreal in April 2011, when he produced a working prototype of the MEMS module, which he is looking forward to testing at the University of Manitoba’s Advanced RF Systems Laboratory in Winnipeg.
The results of this research could greatly benefit chip manufacturers. Kandalaft refers to the “rule of 10” that describes the harsh economics that governs the business of circuit testing. “Finding a fault at a lower level saves you at least 10 times what it would cost to find the fault at the next level,” he says. “That means the cost of testing increases 10 times when it moves from the device to a board, and 10 times again when you move to the system level.”
This innovation yields savings by making it possible to test a chip thoroughly before it becomes part of a larger system. When Kandalaft raised that prospect during a presentation at CMC’s TEXPO research competition in 2010, he was advised to apply for patent protection on the findings. That patent — held by him, Rashidzadeh, Ahmadi, and the university — has since been obtained.
“The students are often the researchers, they’re key players,” Kandalaft concludes. “Advances in technology come from universities where the students are directly involved.”
Rashidzadeh observes that “CMC was the main contributor to the research, providing the necessary tools and fabrication access.” Experience turning theoretical aspects of research into a practical reality and exposure to knowledge transfer is an immense benefit for graduate students.