Dev Systems

RISC-V Processor Design and Prototyping

RISC-V is a free, open instruction set architecture, (ISA) that enables processor innovation through open standard collaboration. The RISC-V ISA provides the research community with an opportunity for innovation in new system products, particularly for machine learning and edge computing. CMC helps realize RISC-V designs by offering: Silicon-proven design platforms based on OpenHW Group CORE-V family …

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FPGA/GPU Cluster

The FPGA/GPU cluster is a cloud-based, remotely accessible compute infrastructure specifically designed to accelerate compute intensive applications, such as machine learning training and inference, video processing, financial computing, database analytics networking and bioinformatics. Latest state of the art acceleration technologies including the Alveo FPGAs, and Tesla V100 GPUs, closely coupled with server processors constitute the …

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Real-time Embedded Systems Lab (RESL)

The Real-time Embedded Systems Lab (RESL) at the University of Waterloo focuses on real-time embedded software and systems that are at the intersection of software technology, embedded networking, and applied formal methods. Real-time embedded systems are characterized by their interaction with the environment through sensors and actuators, their resource-constrained platforms, and non-functional properties. Part of …

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Text description of system controller ports and PXIe expansion card slots pointing to their location on a photo of NI PXI-express chassis.

MIP Si-Photonic Variant

The MIP variant for Si-photonic hardware in the loop bridges the gap between algorithmic/architectural exploration and stimulus, and measurement of photonic hardware in the loop of a prototype microsystem. It presents a modular, desktop environment for Si-photonic chip prototyping in a system context. The platform integrates a PXIe-based control system which includes a system-level design …

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Text description of system controller ports and PXIe expansion card slots pointing to their location on a photo of NI PXI-express chassis.

MIP RF-MEMS Variant

The MIP RF-MEMS variant bridges the gap between algorithmic/analysis and stimulus, and measurement of MEMS RF-MEMS devices. It presents a modular, desktop environment for RF-MEMS and electronics device integration and validation in a system context.  The MIP RF-MEMS variant has a PXIe-based control system, which includes a system-level design environment, RF signal/vector generator, RF signal/vector …

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Text description of system controller ports and PXIe expansion card slots pointing to their location on a photo of NI PXI-express chassis.

MIP Micromirror Variant

The MIP Micromirror variant bridges the gap between algorithmic/analysis and stimulus, and measurement of MEMS micromirror sensors. It presents a modular, desktop environment for MEMS micromirror and electronics device integration and validation in a system context.  The MIP Micromirror variant has a PXIe-based control system, which includes a system-level design environment, data acquisition, FPGA based …

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Text description of system controller ports and PXIe expansion card slots pointing to their location on a photo of NI PXI-express chassis.

MIP Microfluidics Variant

The MIP Microfluidics variant bridges the gap between algorithmic/analysis and stimulus, and measurement of microfluidics bio-sensors and detectors. It presents a modular, desktop environment for microfluidics and electronics device integration and validation in a system context.  The MIP Microfluidics variant has a PXIe-based control system, which includes a system-level design environment, data acquisition, FPGA-based imaging …

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Text description of system controller ports and PXIe expansion card slots pointing to their location on a photo of NI PXI-express chassis.

MIP Generic MEMS Variant

The MIP generic MEMS variant bridges the gap between algorithmic/architectural exploration and stimulus, and measurement of MEMS sensors and actuators. It presents a modular, desktop environment for MEMS and electronics device integration and validation in a system context.  The MIP generic MEMS variant has a PXIe-based control system, which includes a system-level design environment, data …

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Link to internal site: LAB - BEE4 Product Overview

BEE4

High-performance design platforms for system designs that require large FPGA design capacity, memory and I/O bandwidth suitable for a wide range of compute-intensive applications.

Link to internal site: LAB - BEE3 Product Overview

BEE3

High-performance design platforms for system designs that require large FPGA design capacity, memory and I/O bandwidth suitable for a wide range of compute-intensive applications.

Heterogeneous Computing Middleware Platform (HCMP)

Description The Heterogeneous Computing Middleware Platform (HCMP) provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software. Complex tasks such as multi-device memory management, device I/O, kernel scheduling, and dependency management are handled by the platform so that users can focus on writing their applications instead of adhering to complicated specifications. The …

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