Lead User Run of Silicon JFET Transistors Platform

at 1:00 PM

CMC Microsystems and 3IT.Nano at Université de Sherbrooke will present an update about the development of an open-gate silicon JFET platform that enables on-chip integration of functional soft materials with microelectronics.

The platform’s compact form factor is amenable to laboratory testing and integration with other sub-systems (hardware as well as embedded software).

The webinar is an opportunity for participants to provide feedback on features and enhancements that would benefit their research activities.

What you will learn

  • How to become a lead user in the fabrication run planned for spring 2018
  • The PDK based on Tanner L-Edit and the simulation environment in Synopsys Sentaurus
  • The fabrication process and results of process control modules
  • A reference design, using the JFETs with a quantum dot film for ultrasensitive light detection


For more information, contact Andrew Fung or Farouk Azizi.