Typical Kit Contents
- Mask layer information to enable creation of integrated circuit layouts
- DRC (design rule check) rules to check the layout for conformance with manufacturing rules
- Schematic components, circuit simulation models and layout extraction rules to enable simulation of both schematics and layouts
- LVS (layout versus schematic) rules to assist with design verification (do my schematic and layout represent the same circuit?)
- Characterized device libraries with digital logic cells, analog cells, input/output pads, and more
Datasheets on the cells
- Numerous technology files that configure the CAD tools correctly for startup, configuration, maintenance, and bug fixes
- Additional technology files, filter scripts and documentation on exporting a design from Synopsys tools and importing into Cadence tools
- Documentation to assist the user with the design flow. Designs can be captured with the layout editor, schematic editor, HDL (Verilog and VHDL) editors or imported via GDSII, EDIF, Verilog, or VHDL. Output is usually an integrated circuit design in GDSII format, ready for fabrication.
All of this functionality permits full custom design and semi custom design for digital, analog and mixed signal design.
Experimental/Emerging Technologies Kits
* Fabrication services for this process are not available through CMC