Application Note: Mapping the Synopsys ASIP Designer tmicro Processor Example to the Xilinx ML605 FPGA Development Kit

Application Note: Mapping the Synopsys ASIP Designer tmicro Processor Example to the Xilinx ML605 FPGA Development Kit
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Description

The Synopsys ASIP Designer environment enables design exploration of processor architectures, software/application development, simulation, and RTL code generation. This document describes the steps to implement a processor design on a FPGA board using Synopsys ASIP Designer and its RTL generation capabilities. To illustrate this process, the tmicro example design provided in the Synopsys ASIP Designer installation is used. This application note demonstrates a number sorting application running on the ML605, and how to connect a debugger to the processor.

The main steps in this design flow are:

  • Setting up the hardware environment
  • Setting up the development environment
  • Compiling the tmicro Processor Model and Associated Libraries
  • Generating the FPGA Implementation of the tmicro Processor
  • Programming the ML605
  • Debugging the sort Application on the ML605

An optional further step is to debug a simulation target using Modelsim.

Licensing Requirements or Restrictions

All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information, contact our Licensing Administrator at licensing@cmc.ca or 613-530-4787.

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