Microelectronics Design Application Notes

Name Summary
Application Note: Creating a Mask File for TCAD Simulation Using Synopsys IC WorkBench A Graphical Database System (GDS) layout file generated by a third-party CAD tool is imported into Synopsys IC WorkBench. After it is imported, it is adapted and saved in a way that is recognized for use by Synopsys Sentaurus Process.
Application Note: Silicon:Colloidal Quantum Dots JFET for Ultrasensitive Light Detection This application note describes the design, fabrication and integration of Colloidal Quantum Dots with Silicon Junction Field Effect Transistor (CQDs:Si-JFET) for infrared (IR) photodetection.
Application Note: Extracting Two-dimensional Data from Synopsys Sentaurus Simulations Using a Tool Command Language (Tcl) Script This application note provides a Tcl script for decomposing TCAD Sentaurus output files in a *.tdr format into a more easily-read form.
Application Note: Adding Package Libraries to a Cadence Allegro PCB Design XL Project Procedures to add library of CMC supported packages to Cadence Allegro PCB Design XL Project
Application Note: Inter-Reticle Stitching Rules and Constraints for a Wafer-Scale Integrated Circuit This application note describes inter-reticle stitching rules and constraints for a wafer-scale integrated circuit.
Application Note: Physical Design Flow and Techniques for Layout of Wafer-Scale Circuit with Through-Silicon Vias This application note describes a design flow for wafer-scale circuit with through-silicon vias.
Application Note: Using Mentor Tessent Tool for Scan-Based DFT Design with IBM 0.13-µm Technology The application note demonstrates a scan-based design flow via a design example targeting CMOSP13 technology.
Application Note: Top-Down Approach to Design and Simulate Mixed-Signal Chips Using VerilogA/Schematic/Layout Representation A top-down approach to designing mixed-signal microelectronic chips using Cadence Spectre Simulator from Cadence Design Systems, Inc.
Application Note: Using Synopsys Sentaurus to Simulate a P-N Junction This application note describes the use of the Sentaurus software by presenting a simple and practical application: modeling and simulating a Gallium Arsenide (GaAs) p-n junction.
Application Note: Developing Miniature Power Blocks Attached to Wafer-Scaled IC This application note describes the development of miniature power blocks for a wafer-scale IC.
Application Note: Design and Fabrication of a VI-CMOS Image Sensor The design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding.
Application Note: Mixed Fluid-Heat Transfer for Thermal Modeling and Analysis of a Wafer-Scale Integrated Circuit Description of a mixed fluid-heat transfer approach for thermal modeling and thermal analysis
Application Note: Sourcing and Design Considerations for Incorporating Through-Silicon Via on a Wafer-Scale Integrated Circuit Key steps to add a Through Silicon Via (TSV) and extra metal layers to a Complementary Metal Oxide Semiconductor (CMOS) wafer
Application Note: Getting Started on Cadence spectreVerilog Based Mixed-Signal Simulation for TSMC 90NM CMOS (CRN90G PDK) Mixed-signal simulation in Cadence spectreVerilog using TSMC 90-Nanometre (90NM) CRN90G process
Application Note: GA911 Technology Design Flow Details of an analog integrated circuit (IC) design flow using the Gennum GA911 technology
Application Note: ST 65nm LVS—Reconciling Extracted and Schematic Netlists Instructions on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit
Application Note: Using Mentor DFT Tools for Scan-Based DFT Design for IBM 0.13 µm Technology The creation of a scan-based Design-for-Test (DFT) design targeting CMOSP13 technology using Mentor Graphics tools
Application Note: Using Synopsys Sentaurus TCAD Software to Design and Simulate the Electrical Characteristics of a PN Junction Diode Demonstration of the use of software tools in Synopsys Sentaurus TCAD suite, for the design and device simulation of a simple PN junction diode
Application Note: Setting Current EDA Tools to Interpret Design Kits Created for Older EDA Tool Versions Guidance on migrating older digital design kits to accommodate currently supported synthesis and placement and routing tools
Application Note: Backend Digital Design Flow: IBM 0.13um CMOS Technology with Artisan Standard Cell Libraries Description of VLSI digital design flow for the IBM 0.13 µm CMOS process and Artisan StdCell libraries provided by IBM and MOSIS and made available through the Canadian Micro-electronics Corporation (CMC)
Application Note: Measuring Power Consumption of RTL Designs Based on Switching Activity Simulations Calculation of the dynamic and leakage power consumption of VHDL-based designs based on their switching activities
Application Note: Schematic and Post-Layout HSPICE Simulation for STMicroelectronics 90-nanometre CMOS Process Instructions on performing HSPICE simulation of a simple CMOS inverter drawn at the schematic level
Application Note: A Sample-and-Hold Amplifier and an Analog Buffer in DALSA's 0.8 um CMOS Description of the interface to a sample-and-hold amplifier and an analog amplifier, in DALSA's 0.8 µm CMOS technology
Application Note: Simulating Air-Bridges of CPFC GaN MMIC in Momentum A method to model air-bridges in The Canadian Photonics Fabrication Centre (CPFC) GaN MMIC process