After completing the course, students should be able to set up simulations in the framework tool, starting from the mask layout and the fabrication process flow, through to the analysis of simulated DC, transient, and RF behavior of individual devices or small circuits.
The prime target attendees are the ones that are interested in providing training and/or support to other users in their institutions. To be eligible as a trainer you should:
- Be a faculty, student, or research staff from a Canadian Academic Institution.
- Agree to be identified and act as the designated trainer for their research group. For more information, see the Trainer Requirements.
- Have (or have a supervisor with) a Designer or Prototyping Subscription.
Registration is open to academics. Any inquires regarding industrial participation can be directed to Andrew Fung at firstname.lastname@example.org.
- SENTAURUS WORKBENCH: The class covers the basics of this framework tool that allows organization of parameterized TCAD simulations in a single project with many possible splits, or branches.
- SENTAURUS PROCESS: Users will learn the specifics of this process simulation tool, in terms of syntax and introduction of various models to simulate fabrication process flows.
- SENTAURUS STRUCTURE EDITOR: The class will show you how to create 2D and 3D device structures, import structures from a prior process simulation step, make boundary simplifications and properly mesh structures for any subsequent device simulations.
- SENTAURUS DEVICE: The class covers the basics how to simulate the electrical characteristics of devices created with SENTAURUS PROCESS and/or SENTAURUS STRUCTURE EDITOR.
- SENTAURUS VISUAL & INSPECT: Users will be taught how to visualize the structures and results generated from the process and device simulations, using these tools.
At the end of this workshop the student should be able to:
- Run parameterized process and device simulations
- Visualize simulated doping profiles, structure boundaries and materials, I-V curves and internal device characteristics such as carrier densities, current densities, and electric fields.
- Successfully combine mask layouts and process flows to perform simulations of fabrication processes involving single or multiple semiconductors, insulators and metals.
- Select proper models for the simulation of fabrication processes and electrical behavior of devices
- Properly mesh structures for adequate simulations
- Perform AC analyses of RF parameters
To benefit the most from the material presented in this course, you should have a good understanding of the physics involved in the fabrication process of microelectronic devices and/or microelectronic device physics.
Pricing and Registration
The price for the course is $50 for a trainer.
The prime target attendees are the ones that are interested in providing training and/or support for these tools to other users. To those individuals, CMC will provide subsidized travel and accommodations in accordance with the Queen’s University Travel Policy, provided the attendee:
- Agrees to be identified and act as the designated trainer for their research group. See the Trainer Requirements.
- Has a Designer or Prototyping Subscription.
- Is a faculty, student, or research staff from a Canadian Academic Institution.
- Limit 1 per research group
- If you plan to apply for travel subsidy, please read all policies/guidelines/FAQs listed above to ensure that you are qualified for the subsidy and follow the procedures and requirements.
- Original detailed itemized receipts are a mandatory requirement for all travel related expenses, including meals.
See Synopsys Training Location and recommended hotels.
Course cancellations must be received in writing at least one (1) week before the beginning date of the course in question to receive a full refund of the registration fee. A cancellation made after the deadline will not receive a refund. CMC Microsystems makes no commitments on refunds for travel or accommodations.