Modern applications include a variety of heterogeneous circuit blocks. Diverse technologies, substrate and interconnect materials, and processes are required to coexist within a single system. In addition to heterogeneity, ultra‑large scale integration is necessary for a variety of applications, e.g., neuromorphic systems. Silicon interconnect fabric (Si-IF), a wafer scale heterogeneous integration platform, is expected to promote a paradigm shift in the hierarchy of systems integration. The Si-IF platform replaces traditional packaging components, i.e., interposers, packages, and printed circuit boards (PCBs). Bare heterogeneous dies are directly attached to a Si wafer at extremely fine vertical interconnect pitch of 2 to 10 μm and at high proximity of less than 100 μm. The integration is based on thermal compression bonding and therefore solderless. The Si‑IF supports integration of a system-on-wafer (SoW) that exhibits the superior performance of a system-on-chip (SoC), in other words, an SoC-like SoW.
In this webinar, we will describe the Si-IF platform and integration methodology. We will also talk about recent efforts to make the technology available for prototyping and the establishment of the Si-IF technology within a Canadian-based fabrication facility. Eventually, the technology is expected to be accessible through CMC.
Subramanian S. Iyer (Subu) is a Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and architectures that may enable including in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 70 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS as well as the treasurer of EDS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.
Boris Vaisband is currently an Assistant Professor at the Electrical and Computer Engineering Department, McGill University, Montreal, QC, Canada. He received a B.Sc. degree in Computer Engineering from the Technion – Israel Institute of Technology, Haifa, Israel in 2011, and an M.S. and Ph.D. degrees in Electrical Engineering from the University of Rochester, Rochester, NY, in, respectively 2012 and 2017. From 2017 to 2019, he was a Postdoctoral Scholar at the University of California, Los Angeles. Previously, between 2008 and 2011, he held a hardware design position at Intel Corporation in Israel. In the summer of 2013, he interned with the Optical and RF research group at Cisco Systems Inc., San Jose, CA. In the summer of 2015, he interned with the Power Design team at Google Inc., Mountain View, CA. His current research interests are in integration and design methodologies for heterogeneous systems, including power delivery, communication, thermal aware design and floor planning, and noise coupling. Some applications of interest are high-performance computing, Internet of Things devices, and bio-compatible systems.