FAB

Technologies offertes

Grâce à des partenariats avec des fournisseurs, nous offrons des services de plaquettes multi-projets et des services de fabrication connexes par l’entremise de diverses technologies. Consultez notre calendrier de fabrication en ligne.

[Version française disponible sous peu]

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

TSMC 28 nm CMOS Process Technology

Product Page

  • 0.9 V (core)/1.8 V (I/O)
  • 1P9M (1P9M_6x1z1u)
  • High K – Metal gate

$19,450/mm2

$8,775/mm2

TSMC 65 nm CMOS GP

Product Page

  • 1.0 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

$6,350/mm2

$2,350/mm2

TSMC 0.13 μm CMOS

Product Page

  • 1.2 V/3.3 V
  • 1P8M
  • mimcap

Design Kit: TSMC 0.13 µm CMOS

$2,050/mm2

$1,025/mm2

TSMC 65 nm CMOS LP

Product Page

  • 1.2 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

$6,350/mm2

$2,350/mm2

TSMC 0.18 μm CMOS


Product Page

  • 1.8 V/3.3 V
  • 1P6M
  • mimcap
  • LVT/native/HVT

$1,100/mm2

$425/mm2

TSMC 0.35 μm CMOS

Product Page

  • 3.3 V/5 V
  • 2P4M

$1,400/mm2
(Minimum charge is for a 12 mm2 design)

$250/mm2
(Minimum charge is for a 12 mm2 design)

AMS 0.35 μm CMOS – Basic

Product Page

  • 3.3 V/5 V
  • 2P4M

$1,200/mm2

$600/mm2

AMS 0.35 μm CMOS – Opto

Product Page

  • 3.3 V/5 V
  • 2P4M
  • anti-reflective coating

$1,975/mm2

$600/mm2

AMS 0.35 μm CMOS – High Voltage

Product Page

  • 3.3 V/5 V/50 V
  • 2P4MH35B4D3kit includes:
    • standard cell
    • IO
    • bondpad

$2,100/mm2

$600/mm2

Open-Gate Silicon JFET

Product Page

  • JFET with no top gate, enabling user-deposition of sensor material
  • 4-mask process on epitaxial Si with 5 µm feature size
  • Front- and back-side Boron ion implantation
  • One metal routing layer
  • Gold pad metallization (compatible with wirebonding)
  • SiN passivation
  • Aluminum bottom gate

Design Kit: Open-Gate Silicon JFET (OG Si-JFET) in L-Edit and Synopsys Sentaurus

$3,025
(Per 10 x 10 mm2 design)

$1,000
(Per 10 x 10 mm2 design)

Silicon Photonics General-Purpose

Product Page

  • SOI, 220 nm top Si, 2000 nm BOX
  • 193 nm lithography for waveguides
  • 6 implants for optical modulators
  • Ge deposition & implanting for photodetectors
  • Two metal levels for routing plus metal heater

$14,000
(Per 3 x 8 mm2 design)

$5,400
(Per 3 x 8 mm2 design)

GLOBALFOUNDRIES 22FDX FDSOI 22nm Process

Product Page

  • 0.4 V to 0.8 V nominal core voltage
  • 1.2 V / 1.5 V / 1.8 V IO options
  • Four core device Vt’s (FBB, RBB & eLVT)
  • RF BEOL /w ultra thick metal stacks
  • APMOM capacitor
  • GF22FDX-EXT

Contact fab@cmc.ca.

GLOBALFOUNDRIES 45nm RFSOI

Product Page

  • 1 V/1.5 V/1.8 V
  • 1P8M process
  • Native/HVT/SVT/UVT FETs
  • N+ silicide resistor
  • Vertical natural capacitor
  • BEOL inductors
  • Thin oxide Varactor
  • ft/fmax 290/410 GHz
  • 45RFSOI-RF V1.2_0.2

Contact fab@cmc.ca.

GLOBALFOUNDRIES 90nm BiCMOS SiGe 9HP

Product Page

  • 1.2 V/1.8 V/2.5 V/3.3 V 
  • 1P10M process 
  • Native/HVT FETs 
  • ft/fmax 310/370GHz 
  • Twin_ or triple_well (NFET in isolated pwell) CMOS technology 
  • MIM/Dual/high Q MIM capcitors 
  • Series/Parallel spirals Inductors 
  • PIN / Schottky Barrier diode 
  • 90HPSIGE-9HP  V1.3_0.0

Contact fab@cmc.ca.

GLOBALFOUNDRIES SiGe 8XP BiCMOS 130nm

Product Page

  • 2 V/2.5 V Core voltage
  • 5 V/3.3 V IO voltage
  • 5 metal base stack, with the option to 8 levels of metallization
  • High performance enhanced FET
  • Ft/fmax 250/340 GHz
  • MIM and Dual MIM
  • Regular Vt and Triple well FET options
  • Series/Parallel spirals Inductors
  • µm/mm wave passive components
  • Thin/Thick dual gate oxide

Contact fab@cmc.ca.

GLOBALFOUNDRIES 130nm BiCMOS SiGe 8HP

Product Page

Due to low-demand, Global Foundries will no longer be offering this technology.  As an alternate technology, please consider the higher-performance 8XP flavour.

Contact fab@cmc.ca.

GLOBALFOUNDRIES 90nm CMOS-photonics 9WG

Product Page

  • SOI substrate
  • Far-BEOL V-groove for fibre attach
  • 1P7M
  • LVT

Contact fab@cmc.ca.

III-V Epitaxy on GaAs Substrates, InP and Ge Substrates

Product Page

  • Provide III – V materials to fabricate
  • Lasers, LEDs and SOAs on InP substrate
  • VCSELs, nonlinear optics and high-mobility devices on GaAs substrate
  • Multi-junction solar cells and converters on Ge substrate
  • MOCVD epitaxy of InGaAs, InGaAsP and InAlGaAs lattice-matched and strained MQW and Quantum Dot materials on 3” InP substrate
  • MBE epitaxy of high purity InGaAs, InAlAs and InP material on 2” InP substrate
  • MOCVD epitaxy of InGaAs, AlGaAs, InAlGaAs lattice-matched and strained MQW materials on 3” and 4” GaAs substrates
  • MBE epitaxy of high purity GaAs, AlGaAs, and exotic alloys on 3” GaAs substrate
  • MOCVD epitaxy of GaAs, AlGaAs, AlInP, InGaP, InGaAs and AlInGaAs on 6” Ge substrate
  • Wafer deliverables will go with the standard metrologies of photoluminescence (PL) and x-ray diffraction
  • Other epitaxy metrologies are available with additional fees

The cost is highly structural dependent. Please contact zhang@cmc.ca.

MEMSCAP PiezoMUMPs

Product Page

  • SOI MEMS
  • 25um structure layer
  • piezoelectric metal

$2,325
(per 5 x 5 mm2 design) 

$550
(per 5 x 5 mm2 design) 

MEMSCAP PolyMUMPs Multi-User MEMS Process Technology

Product Page

  • Surface MEMS
  • Three structure layers

$2,325
(per 5 x 5 mm2 design) 

$550
(per 5 x 5 mm2 design) 

MEMSCAP Post-Processing for PolyMUMPs

Product Page

$825/design

$325/design

Teledyne DALSA MIDIS Platform

Product Page

  • Getter-free high-vacuum sealing allows resonator Q factors > 20,000
  • Efficient wafer-level packaging minimizes overall die size
  • 1.5-μm feature size in a 30-μm thick membrane
  • Comb height control allows out-of-plane sensing
  • TSV allows compact design ready for co-packaging
  • Deliver 40 copies for each design
  • Sealed-cavity MEMS
  • 30-μm structure layer
  • High-vacuum

Teledyne DALSA MIDIS Design Kits

$9,800
(per 4 x 4 mm2 design) 

$4,250
(per 4 x 4 mm2 design) 

MicraGEM-Si™ MEMS Process

Product Page

  • Two thick SOI structure layers with up to three functional levels of silicon thickness option. This enables structures such as vertical comb-drive actuators.
  • Base and top device layers are electrically connected through the bond interface, allowing 3D routing of electrical signals.
  • Patterned low-stress gold metallization on the top surface is suited for highly reflective mirrors and contact pads for gold wire bonding.
  • Available in sizes 4 mm x 4 mm, 4 mm x 8 mm, and 8 mm x 8 mm
  • SOI MEMS
  • Two structure layers
  • Three trench depths

Contact fab@cmc.ca.

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

TSMC 28 nm CMOS Process Technology

Product Page

  • 0.9 V (core)/1.8 V (I/O)
  • 1P9M (1P9M_6x1z1u)
  • High K – Metal gate

$19,450/mm2

$8,775/mm2

TSMC 65 nm CMOS GP

Product Page

  • 1.0 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

$6,350/mm2

$2,350/mm2

TSMC 0.13 μm CMOS

Product Page

  • 1.2 V/3.3 V
  • 1P8M
  • mimcap

Design Kit: TSMC 0.13 µm CMOS

$2,050/mm2

$1,025/mm2

TSMC 65 nm CMOS LP

Product Page

  • 1.2 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

$6,350/mm2

$2,350/mm2

TSMC 0.18 μm CMOS


Product Page

  • 1.8 V/3.3 V
  • 1P6M
  • mimcap
  • LVT/native/HVT

$1,100/mm2

$425/mm2

TSMC 0.35 μm CMOS

Product Page

  • 3.3 V/5 V
  • 2P4M

$1,400/mm2
(Minimum charge is for a 12 mm2 design)

$250/mm2
(Minimum charge is for a 12 mm2 design)

AMS 0.35 μm CMOS – Basic

Product Page

  • 3.3 V/5 V
  • 2P4M

$1,200/mm2

$600/mm2

AMS 0.35 μm CMOS – Opto

Product Page

  • 3.3 V/5 V
  • 2P4M
  • anti-reflective coating

$1,975/mm2

$600/mm2

AMS 0.35 μm CMOS – High Voltage

Product Page

  • 3.3 V/5 V/50 V
  • 2P4MH35B4D3kit includes:
    • standard cell
    • IO
    • bondpad

$2,100/mm2

$600/mm2

GLOBALFOUNDRIES 22FDX FDSOI 22nm Process

Product Page

  • 0.4 V to 0.8 V nominal core voltage
  • 1.2 V / 1.5 V / 1.8 V IO options
  • Four core device Vt’s (FBB, RBB & eLVT)
  • RF BEOL /w ultra thick metal stacks
  • APMOM capacitor
  • GF22FDX-EXT

Contact fab@cmc.ca.

GLOBALFOUNDRIES 45nm RFSOI

Product Page

  • 1 V/1.5 V/1.8 V
  • 1P8M process
  • Native/HVT/SVT/UVT FETs
  • N+ silicide resistor
  • Vertical natural capacitor
  • BEOL inductors
  • Thin oxide Varactor
  • ft/fmax 290/410 GHz
  • 45RFSOI-RF V1.2_0.2

Contact fab@cmc.ca.

GLOBALFOUNDRIES 90nm BiCMOS SiGe 9HP

Product Page

  • 1.2 V/1.8 V/2.5 V/3.3 V 
  • 1P10M process 
  • Native/HVT FETs 
  • ft/fmax 310/370GHz 
  • Twin_ or triple_well (NFET in isolated pwell) CMOS technology 
  • MIM/Dual/high Q MIM capcitors 
  • Series/Parallel spirals Inductors 
  • PIN / Schottky Barrier diode 
  • 90HPSIGE-9HP  V1.3_0.0

Contact fab@cmc.ca.

GLOBALFOUNDRIES SiGe 8XP BiCMOS 130nm

Product Page

  • 2 V/2.5 V Core voltage
  • 5 V/3.3 V IO voltage
  • 5 metal base stack, with the option to 8 levels of metallization
  • High performance enhanced FET
  • Ft/fmax 250/340 GHz
  • MIM and Dual MIM
  • Regular Vt and Triple well FET options
  • Series/Parallel spirals Inductors
  • µm/mm wave passive components
  • Thin/Thick dual gate oxide

Contact fab@cmc.ca.

GLOBALFOUNDRIES 130nm BiCMOS SiGe 8HP

Product Page

Due to low-demand, Global Foundries will no longer be offering this technology.  As an alternate technology, please consider the higher-performance 8XP flavour.

Contact fab@cmc.ca.

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

Silicon Photonics General-Purpose

Product Page

  • SOI, 220 nm top Si, 2000 nm BOX
  • 193 nm lithography for waveguides
  • 6 implants for optical modulators
  • Ge deposition & implanting for photodetectors
  • Two metal levels for routing plus metal heater

$14,000
(Per 3 x 8 mm2 design)

$5,400
(Per 3 x 8 mm2 design)

GLOBALFOUNDRIES 90nm CMOS-photonics 9WG

Product Page

  • SOI substrate
  • Far-BEOL V-groove for fibre attach
  • 1P7M
  • LVT

Contact fab@cmc.ca.

III-V Epitaxy on GaAs Substrates, InP and Ge Substrates

Product Page

  • Provide III – V materials to fabricate
  • Lasers, LEDs and SOAs on InP substrate
  • VCSELs, nonlinear optics and high-mobility devices on GaAs substrate
  • Multi-junction solar cells and converters on Ge substrate
  • MOCVD epitaxy of InGaAs, InGaAsP and InAlGaAs lattice-matched and strained MQW and Quantum Dot materials on 3” InP substrate
  • MBE epitaxy of high purity InGaAs, InAlAs and InP material on 2” InP substrate
  • MOCVD epitaxy of InGaAs, AlGaAs, InAlGaAs lattice-matched and strained MQW materials on 3” and 4” GaAs substrates
  • MBE epitaxy of high purity GaAs, AlGaAs, and exotic alloys on 3” GaAs substrate
  • MOCVD epitaxy of GaAs, AlGaAs, AlInP, InGaP, InGaAs and AlInGaAs on 6” Ge substrate
  • Wafer deliverables will go with the standard metrologies of photoluminescence (PL) and x-ray diffraction
  • Other epitaxy metrologies are available with additional fees

The cost is highly structural dependent. Please contact zhang@cmc.ca.

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

MEMSCAP PiezoMUMPs

Product Page

  • SOI MEMS
  • 25um structure layer
  • piezoelectric metal

$2,325
(per 5 x 5 mm2 design) 

$550
(per 5 x 5 mm2 design) 

MEMSCAP PolyMUMPs Multi-User MEMS Process Technology

Product Page

  • Surface MEMS
  • Three structure layers

$2,325
(per 5 x 5 mm2 design) 

$550
(per 5 x 5 mm2 design) 

MEMSCAP Post-Processing for PolyMUMPs

Product Page

$825/design

$325/design

Teledyne DALSA MIDIS Platform

Product Page

  • Getter-free high-vacuum sealing allows resonator Q factors > 20,000
  • Efficient wafer-level packaging minimizes overall die size
  • 1.5-μm feature size in a 30-μm thick membrane
  • Comb height control allows out-of-plane sensing
  • TSV allows compact design ready for co-packaging
  • Deliver 40 copies for each design
  • Sealed-cavity MEMS
  • 30-μm structure layer
  • High-vacuum

Teledyne DALSA MIDIS Design Kits

$9,800
(per 4 x 4 mm2 design) 

$4,250
(per 4 x 4 mm2 design) 

MicraGEM-Si™ MEMS Process

Product Page

  • Two thick SOI structure layers with up to three functional levels of silicon thickness option. This enables structures such as vertical comb-drive actuators.
  • Base and top device layers are electrically connected through the bond interface, allowing 3D routing of electrical signals.
  • Patterned low-stress gold metallization on the top surface is suited for highly reflective mirrors and contact pads for gold wire bonding.
  • Available in sizes 4 mm x 4 mm, 4 mm x 8 mm, and 8 mm x 8 mm
  • SOI MEMS
  • Two structure layers
  • Three trench depths

Contact fab@cmc.ca.

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

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