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MIP Si-Photonic Variant

The MIP variant for Si-photonic hardware in the loop bridges the gap between algorithmic/architectural exploration and stimulus, and measurement of photonic hardware in the loop of a prototype microsystem. It presents a modular, desktop environment for Si-photonic chip prototyping in a system context.

The platform integrates a PXIe-based control system which includes a system-level design environment, data acquisition, FPGA based signal/control processing, and power supplies, with generic optical source and detection modules and a feedback-controlled optical fibre alignment system.

Benefits

Accelerates research by providing a feature-rich platform for integration and validating of Si-photonic-based microsystems.
Addresses specific research needs through a graphics-based programmable environment and hardware enabling integration of Si-photonic hardware in the loop.
Enables a faster path to commercialization by sourcing commercial-grade components and through compliance with commercial standards and interfaces (e.g., PXI and PXIe).

Applications

A block diagram and photos of this prototype MIP variant are shown below. The photo at the right shows a fibre array aligned to Si-photonic device, with an inset of the resonator transmission spectrum measured using the MIP coupled to an Agilent 81600B tunable source.

Possible research applications include control of Si-photonic-based ring resonators and sensors for biomedical applications, and Micro-Opto-Electro-Mechanical Systems (MOEMS) such as optical gyroscopes or accelerometers, under real-time feedback control.

Features

PXI-express base, which includes:

System controller, standard and real time operating systems
PXIe expansion card slots, including high-end FPGA-based DAQ, high-resolution digitizer, waveform generator, and programmable power supply
Program environment: LabVIEW, C/C++

The PXI system hub is complemented with instruments enabling incorporation of Si-photonic hardware in the loop:

Custom Micronix motion control stage optimized for automated optical coupling to Si-photonic surface grating arrays:
- 100-mm in-plane axis (X, Y) travel, with 50-nm precision. Maximum speed: 5 mm/s
- Typical sample loading time: less than 15 minutes, including carrier flatness/angle adjustments and 2 minutes alignment
- Viewing optics to aid in optical alignment
- PLC Connections 8 PM fibre bundle to interface to Si-photonic chip surface gratings
Agilent N7711A-210 tunable laser, controlled via USB by the MIP PXI-based controller:
- +15 dBm output
- 100 kHz linewidth over 1527.60 nm to 1565.50 nm tuning range
Agilent N7744A multiport optical power meter, USB interface:
- Four InGaAs sensor ports with 1250 to 1650 nm wavelength range
Temperature controller with up to 0.001°C stability

Resources

Technical documents
- User Guide: Setting up MIP for Silicon Photonic Hardware-in-the-loop
Reference design
- User Guide: MIP for Silicon Photonic Hardware-in-the-loop Reference Design
Generic autoalignment software (contact CMC for MIP-specific version of this code)
- http://siepic.ubc.ca/probestation
Webinar
- MIP for Si Photonic HW-in-the-loop, reference design webinar
Videos
- Si-P MIP autoalignment and test automation example
- https://youtu.be/R0Tbjth_d-Y

How to Access

Susan Xu
Senior Engineer, System-Level Integration
Phone: +1.613.530.4692
E-mail Susan Xu

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