Multi-User Run of Silicon JFET Transistors Platform

February 28, 2020 @ 2:00 pm EST

CMC Microsystems and 3IT.Nano at Université de Sherbrooke have developed an open-gate silicon JFET platform that enables on-chip integration of functional soft materials with microelectronics. The platform’s compact form factor is amenable to laboratory testing and integration with other sub-systems (hardware as well as embedded software).

This webinar will describe

-How to become a designer in the fabrication run planned for April, 2020
-The PDK based on Tanner L-Edit and the simulation environment in Synopsys Sentaurus
-The fabrication process and results of process control modules
-A reference design, using the JFETs with a quantum dot film for ultrasensitive light detection
-Planned development of fluidic interfaces for bioassays

The webinar is an opportunity for participants to provide feedback on features and enhancements that would benefit their research activities.


View the Open-Gate Silicon JFET product page

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