Benefits
- Accelerates research by providing
- A feature-rich platform for implementing and validating Software Defined Radio system architectures and algorithms
- An automated design flow from MATLAB/Simulink (and/or proprietary software), reducing development effort and enabling platform use by application/domain experts
- Addresses specific research needs through a hardware/software programmable system, in particular:
- High-performance Digital Signal Processing (DSP)
- Hardware-based application acceleration
- Enables a faster path to commercialization by sourcing commercial-grade components and through compliance with commercial standards and interfaces (e.g., PCI-express, Ethernet).
- Technical support and training from CMC Microsystems
Applications
- Multi-channel wireless system prototyping:
- Cellular
- WiFi
- L-/S-band SATCOM
- Massive MIMO communications testbeds
- MIMO RADAR systems
- Cognitive radio networks
- White space radios
Resources
Features
nanoBEE SDR
- Xilinx Zynq Z-7100
- 1 or 2 FMC112 modules for 2×2 and 4×4 MIMO respectively:
- Up to 56 MHz bandwidth per channel
- RF range covers 70 MHz to 6 GHz
- 23 dBm output power (2.3~2.7 GHz, 3.3~3.8 GHz and 4.9~5.9 GHz)
- -94 dBm receiver sensitivity level
- GPS module w/ external antenna connection
- QSFP+ and 4 SFP+ connectors for up to 80Gbits of optical IO
- HDMI IN/OUT
- 2 AuxIO connectors:
- 8 GPIO + Clk_in + Clk_out per connector (100MHz max)
- UART/JTAG for debugging
- 1GbE for remote log in and management of the nanoBEE
- Jitter cleaner for clock recovery and synchronization applications
- Portable form factor
megaBEE SDR (8×8 / 16×16)
- Eight wideband RF channels:
- Up to 56 MHz bandwidth per channel
- RF range covers 70 MHz to 6 GHz
- 23 dBm output power (2.3~2.7 GHz, 3.3~3.8 GHz and 4.9~5.9 GHz)
- -94 dBm receiver sensitivity level
- Two Xilinx Zynq Z-7100 FPGAs with four ARM cores and 4040 DSP slices
- Optimized for LTE and 5G cellular RF bands worldwide
- Flexible MIMO SDR architecture
- Clock architectures:
- Flexible clock sources (19.2 MHz or 40 MHz)
- Ultra-low jitter cleaner (<1ps RMS jitter) and clock distribution
- Sub-ns accuracy clock synchronization based on IEEE 1588v2 protocol
- SDR software compatibility:
- HDL
- MATLAB/Simulink
- C/C++/Python
- Peripherals:
- 2 GB DDR3 and 8GB Flash Memory
- 8x SFP+
- 2x QSFP
- 2x HDMI IN and OUT
- 2x USB v 2.0 (Host)
- 2x RJ-45 (1G Ethernet)
- Compact 1U form factor