FAB

TSMC 0.18 µm CMOS Process Technology

Description

CMC’s multi-project wafer service delivers Taiwan Semiconductor Manufacturing Company (TSMC) nanometer and micron-scale CMOS technologies.

This 0.18 μm CMOS technology is offered with a robust design kit (with a commercial cell library) that supports RF, analog, mixed-signal and digital design flows, plus various tutorials that use this technology for the design example.

Process Details

  • Electrical Contact
  • Forming Technology: Salicide
  • Layers: 6 metal, 1 poly
  • Supply Voltages: 1.8 V and 3.3 V
  • Minimum Drawn Gate Length: 0.18 μm
  • Options:
    • Logic (default)
    • Mixed-signal (deep N-well and metal-insulator-metal [MiM] capacitor)
    • Thick metal

Note: The expected number of chips to be delivered for this technology is 40.

Features

  • 1.8 V/3.3 V
  • 1P6M
  • mimcap
  • LVT/native/HVT

Applications

The 0.18 µm CMOS (CMC term is CMOSP18) process is suitable for:

  • Analog circuits
  • Full custom digital circuits
  • RF circuits
  • Mixed-signal circuits

Pricing

Canadian Academic

$1,100/mm2
(Minimum charge is for a 1.1 x 1.1 mm2 design)

Canadian Academic Peer Reviewed

$425/mm2
(Minimum charge is for a 1.1 x 1.1 mm2 design)

SponsorChip helps companies enhance their research efforts and links to academic researchers.

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