TSMC 0.18 µm CMOS Process Technology
CMC’s multi-project wafer service delivers Taiwan Semiconductor Manufacturing Company (TSMC) nanometer and micron-scale CMOS technologies.
This 0.18 μm CMOS technology is offered with a robust design kit (with a commercial cell library) that supports RF, analog, mixed-signal and digital design flows, plus various tutorials that use this technology for the design example.
- Electrical Contact
- Forming Technology: Salicide
- Layers: 6 metal, 1 poly
- Supply Voltages: 1.8 V and 3.3 V
- Minimum Drawn Gate Length: 0.18 μm
- Logic (default)
- Mixed-signal (deep N-well and metal-insulator-metal [MiM] capacitor)
- Thick metal
Note: The expected number of chips to be delivered for this technology is 40.
- 1.8 V/3.3 V
The 0.18 µm CMOS (CMC term is CMOSP18) process is suitable for:
- Analog circuits
- Full custom digital circuits
- RF circuits
- Mixed-signal circuits
- Design Kit: TSMC 0.18µm CMOS Process
- Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows
- Design Library: ARM Digital Standard Cell and IO Libraries for TSMC 0.18 µm CMOS
- Design Library: TSMC 0.18 µm CMOS Standard Cells Library – tsmc-cl018g_sc-x_2004q3v1
- Design Flow: Digital IC Design (from RMC)