CAD

Design Kits

  • Mask layer information to enable creation of integrated circuit layouts
  • DRC (design rule check) rules to check the layout for conformance with manufacturing rules
  • Schematic components, circuit simulation models and layout extraction rules to enable simulation of both schematics and layouts
  • LVS (layout versus schematic) rules to assist with design verification (do my schematic and layout represent the same circuit?)
  • Characterized device libraries with digital logic cells, analog cells, input/output pads, and more Datasheets on the cells
  • Numerous technology files that configure the CAD tools correctly for startup, configuration, maintenance, and bug fixes
  • Additional technology files, filter scripts and documentation on exporting a design from Synopsys tools and importing into Cadence tools
  • Documentation to assist the user with the design flow. Designs can be captured with the layout editor, schematic editor, HDL (Verilog and VHDL) editors or imported via GDSII, EDIF, Verilog, or VHDL. Output is usually an integrated circuit design in GDSII format, ready for fabrication.

All of this functionality permits full custom design and semi custom design for digital, analog and mixed signal design.

Design kits typically consist of technology files and device libraries. Combined with the CAD tool, kits allow you to design an integrated circuit in a specific process technology. Analog and digital circuit design and layout are usually supported.

Experimental/Emerging Technologies Kits

Design Kit or ProcessCAD Tools Supported or Required
Interposer Platform PDK for 2.5D IntegrationTanner L-Edit and S-Edit
Open-Gate Silicon JFETTanner L-Edit and Synopsys Sentaurus

MEMS Kits

Design Kit or ProcessCAD Tools Supported or RequiredNameSummary
Teledyne DALSA MIDISTanner L-Edit, Cadence, CoventorWareDesign Kit: Teledyne DALSA MIDIS Platform V1P4, for Tanner L-EditTeledyne DALSA MIDIS™ design kit for Tanner L-Edit.
  Design Kit: Teledyne DALSA MIDIS Platform V1P4, for CadenceTeledyne DALSA MEMS Integrated Design for Inertial Sensors (MIDIS™) platform, for Cadence
  Design Kit: Teledyne DALSA MIDIS Platform V1P4, for CoventorwareTeledyne DALSA MEMS Integrated Design for Inertial Sensors (MIDIS™) platform, for CoventorWare
  Design Guide: Teledyne DALSA MIDIS Platform V1P4This document provides information and design rules to be used for design and physical layout of Inertial Sensors manufactured using TELEDYNE DALSA’s 1.5μm, Bulk Silicon Micromachining Inertial Sensors Technology with WLCSP under vacuum.
Design Kit or ProcessCAD Tools Supported or RequiredNameSummary
Micralyne MicraGEM-SiTanner L-EditDesign Kit: Micralyne MicraGEM-Si™, for Tanner L-EditMicralyne MicraGEM-Si design kit for Tanner L-Edit
  Design Handbook: Micralyne MicraGEM-Si™ (ICI-319)This Design Handbook contains technology summary and the design rules of the MicraGEM-Si MEMS process.
Design Kit or ProcessCAD Tools Supported or RequiredNameSummary
MEMSCAP PiezoMUMPsTanner L-Edit, MEMS Pro, CoventorWarDesign Kit: PiezoMUMPs for CoventorwareMEMSCAP PiezoMUMPs process is introduced in response to increasing research and interest in Piezoelectric MEMS devices.
  Design Kit: MEMSCAP PiezoMUMPs Design HandbookMEMSCAP PiezoMUMPs process is introduced in response to increasing research and interest in Piezoelectric MEMS devices.
MEMSCAP PolyMUMPsMEMS Pro, CoventorWareDesign Kit: PolyMUMPs MEMS Process for CoventorWareThis release contains the design kit for the MEMSCAP PolyMUMPs fabrication process and the CoventorWare design tool.
  Design Kit: PolyMUMPs Design Handbook for MEMSProDesign Handbook with process details and design rules/consideration

Microsystems Kits

Design Kit or ProcessCAD Tools Supported or RequiredName (if multiple offerings)Summary
TSMC 65 nm CMOS GPCadenceDesign Kit: TSMC 65 nm CMOS GP – CRN65GPA mixed-signal/RF 1P9M low-power process configured for 1.0/2.5V and ultra-thick (34kA) top metal options
  Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od31.0V/2.5V standard digital I/O for TSMC 65nm general-purpose CMOS process
  Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplusStandard cell libraries for TSMC 65nm general-purpose CMOS 1.0V/2.5V process
  Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65vBond pad library for TSMC 65nm general-purpose CMOS (to be used with tpzn65gpgv2)
TSMC 65 nm CMOS LPCadenceDesign Kit: TSMC 65 nm CMOS LP – CRN65LPAccess to a design kit for the TSMC 65nm CMOS process—mixed-signal/RF 1P9M low-power process configured for 1.2/2.5V and ultra-thick (34kA) top metal options
TSMC 0.13 µm CMOSCadence  
TSMC 0.18 µm CMOSCadenceDesign Kit: TSMC 0.18 µm CMOS ProcessA 0.18-µm single poly six metal salicide CMOS process.
  Design Library: TSMC 0.18 µm CMOS ModelsLogic and circuit models from various suppliers including TSMC.
  Design Library: ARM Digital Standard Cell and IO Libraries for TSMC 0.18 µm CMOSARM (formerly Artisan) Standard Cell and Digital IO Libraries for TSMC 0.18µm CMOS CM018 1.8V/3.3V process
  Design Library: TSMC 0.18 µm CMOS Standard Cells Library – tsmc-cl018g_sc-x_2004q3v1Standard cell library for TSMC 0.18µm CMOS CM018 1.8V process
TSMC 0.35 µm CMOSCadence  
Design Kit or ProcessCAD Tools Supported or RequiredName (if multiple offerings)Summary
STM 28 nm CMOS FD SOICadence  
Design Kit or ProcessCAD Tools Supported or Required
AMS 0.35 µm CMOSCadence
Analog/Mixed Signal DesignCadence

Photonics Kits

Design Kit or ProcessCAD Tools Supported or Required
CMC/CPFC III-VDesign Workshop dw-2000
AMF Si PhotonicsMentor Graphics Pyxis
Silicon Photonics Design PlatformLuceda IPKISS.EDA, Tanner L-Edit and S-Edit
AMF Silicon PhotonicsMentor Graphics L-Edit Photonics

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