CAD

Design Kits

  • Mask layer information to enable creation of integrated circuit layouts
  • DRC (design rule check) rules to check the layout for conformance with manufacturing rules
  • Schematic components, circuit simulation models and layout extraction rules to enable simulation of both schematics and layouts
  • LVS (layout versus schematic) rules to assist with design verification (do my schematic and layout represent the same circuit?)
  • Characterized device libraries with digital logic cells, analog cells, input/output pads, and more Datasheets on the cells
  • Numerous technology files that configure the CAD tools correctly for startup, configuration, maintenance, and bug fixes
  • Additional technology files, filter scripts and documentation on exporting a design from Synopsys tools and importing into Cadence tools
  • Documentation to assist the user with the design flow. Designs can be captured with the layout editor, schematic editor, HDL (Verilog and VHDL) editors or imported via GDSII, EDIF, Verilog, or VHDL. Output is usually an integrated circuit design in GDSII format, ready for fabrication.

All of this functionality permits full custom design and semi custom design for digital, analog and mixed signal design.

Design kits typically consist of technology files and device libraries. Combined with the CAD tool, kits allow you to design an integrated circuit in a specific process technology. Analog and digital circuit design and layout are usually supported.

Experimental/Emerging Technologies Kits

Design Kit or Process CAD Tools Supported or Required
Interposer Platform PDK for 2.5D Integration Tanner L-Edit and S-Edit
Open-Gate Silicon JFET Tanner L-Edit and Synopsys Sentaurus

MEMS Kits

Design Kit or Process CAD Tools Supported or Required Name Summary
Teledyne DALSA MIDIS Tanner L-Edit, Cadence, CoventorWare Design Kit: Teledyne DALSA MIDIS Platform V1P4, for Tanner L-Edit Teledyne DALSA MIDIS™ design kit for Tanner L-Edit.
Design Kit: Teledyne DALSA MIDIS Platform V1P4, for Cadence Teledyne DALSA MEMS Integrated Design for Inertial Sensors (MIDIS™) platform, for Cadence
Design Kit: Teledyne DALSA MIDIS Platform V1P4, for Coventorware Teledyne DALSA MEMS Integrated Design for Inertial Sensors (MIDIS™) platform, for CoventorWare
Design Guide: Teledyne DALSA MIDIS Platform V1P4 This document provides information and design rules to be used for design and physical layout of Inertial Sensors manufactured using TELEDYNE DALSA’s 1.5μm, Bulk Silicon Micromachining Inertial Sensors Technology with WLCSP under vacuum.
Design Kit or Process CAD Tools Supported or Required Name Summary
Micralyne MicraGEM-Si Tanner L-Edit Design Kit: Micralyne MicraGEM-Si™, for Tanner L-Edit Micralyne MicraGEM-Si design kit for Tanner L-Edit
Design Handbook: Micralyne MicraGEM-Si™ (ICI-319) This Design Handbook contains technology summary and the design rules of the MicraGEM-Si MEMS process.
Design Kit: PiezoMUMPs for Tanner L-Edit and MEMS Pro MEMSCAP PiezoMUMPs process is introduced in response to increasing research and interest in Piezoelectric MEMS devices.
Design Kit or Process CAD Tools Supported or Required Name Summary
MEMSCAP PiezoMUMPs Tanner L-Edit, MEMS Pro, CoventorWar Design Kit: PiezoMUMPs for Coventorware MEMSCAP PiezoMUMPs process is introduced in response to increasing research and interest in Piezoelectric MEMS devices.
Design Kit: MEMSCAP PiezoMUMPs Design Handbook MEMSCAP PiezoMUMPs process is introduced in response to increasing research and interest in Piezoelectric MEMS devices.
MEMSCAP PolyMUMPs MEMS Pro, CoventorWare Design Kit: PolyMUMPs MEMS Process for CoventorWare This release contains the design kit for the MEMSCAP PolyMUMPs fabrication process and the CoventorWare design tool.
Design Kit: PolyMUMPs Design Handbook for MEMSPro Design Handbook with process details and design rules/consideration

Microsystems Kits

Design Kit or Process CAD Tools Supported or Required Name (if multiple offerings) Summary
TSMC 65 nm CMOS GP Cadence Design Kit: TSMC 65 nm CMOS GP – CRN65GP A mixed-signal/RF 1P9M low-power process configured for 1.0/2.5V and ultra-thick (34kA) top metal options
Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 1.0V/2.5V standard digital I/O for TSMC 65nm general-purpose CMOS process
Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Standard cell libraries for TSMC 65nm general-purpose CMOS 1.0V/2.5V process
Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Bond pad library for TSMC 65nm general-purpose CMOS (to be used with tpzn65gpgv2)
TSMC 65 nm CMOS LP Cadence Design Kit: TSMC 65 nm CMOS LP – CRN65LP Access to a design kit for the TSMC 65nm CMOS process—mixed-signal/RF 1P9M low-power process configured for 1.2/2.5V and ultra-thick (34kA) top metal options
TSMC 0.13 µm CMOS Cadence
TSMC 0.18 µm CMOS Cadence Design Kit: TSMC 0.18 µm CMOS Process A 0.18-µm single poly six metal salicide CMOS process.
Design Library: TSMC 0.18 µm CMOS Models Logic and circuit models from various suppliers including TSMC.
Design Library: ARM Digital Standard Cell and IO Libraries for TSMC 0.18 µm CMOS ARM (formerly Artisan) Standard Cell and Digital IO Libraries for TSMC 0.18µm CMOS CM018 1.8V/3.3V process
Design Library: TSMC 0.18 µm CMOS Standard Cells Library – tsmc-cl018g_sc-x_2004q3v1 Standard cell library for TSMC 0.18µm CMOS CM018 1.8V process
TSMC 0.35 µm CMOS Cadence
Design Kit or Process CAD Tools Supported or Required Name (if multiple offerings) Summary
STM 28 nm CMOS FD SOI Cadence
Design Kit or Process CAD Tools Supported or Required
AMS 0.35 µm CMOS Cadence
Analog/Mixed Signal Design Cadence

Photonics Kits

Design Kit or Process CAD Tools Supported or Required
CMC/CPFC III-V Design Workshop dw-2000
AMF Si Photonics Mentor Graphics Pyxis
Silicon Photonics Design Platform Luceda IPKISS.EDA, Tanner L-Edit and S-Edit

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