FAB

Available Technologies

Through supplier partnerships, we offer multi-project wafer services and related fabrication services in a variety of technologies. View our fabrication schedule online.
Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

STM 28 nm CMOS FDSOI

ST Microelectronics logo

Product Page

  • 1.0/1.8V
  • 1P8M
  • no mimcap
  • LVT

RF_mmW_6U1x_2T8x_LB

kit includes:

  • standard cell
  • IO
  • bondpad

Libraries:

  • custom memory generator

$12,500/mm2

(Minimum charge is for a 1.25mm2 design)

$5,000/mm2

(Minimum charge is for a 1.25mm2 design)

TSMC 65 nm CMOS GP

Product Page

  • 1.0/2.5V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

CRN65GP

Libraries:

  • standard cell
  • IO
  • bondpad
  • memory generator

$5,200/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$2,350/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design.)

TSMC 65 nm CMOS LP

Product Page

  • 1.2/2.5V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

CRN65LP

Libraries:

  • standard cell
  • IO
  • bondpad

$5,200/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$2,350/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

TSMC 0.13 μm CMOS

Product Page

  • 1.2/3.3V
  • 1P8M
  • mimcap

 

CR013G

Libraries:

  • standard cells
  • IO
  • bondpad

$2,050/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$1,025/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

TSMC 0.18 μm CMOS


Product Page

  • 1.8/3.3V
  • 1P6M
  • mimcap
  • LVT/native/HVT

CM013G

Libraries:

  • standard cell
  • IO
  • bondpad

$1,100/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$425/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

TSMC 0.35 μm CMOS

Product Page

  • 3.3/5V
  • 2P4M

$475/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$250/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

AMS 0.35 μm CMOS – Basic

Product Page

  • 3.3/5V
  • 2P4M

C35B4C3

kit includes:

  • standard cell
  • IO
  • bondpad
  • analog blocks

$1,200/mm2

$600/mm2

AMS 0.35 μm CMOS – Opto

Product Page

  • 3.3/5V
  • 2P4M
  • anti-reflective coating

C35B4O1

kit includes:

  • standard cell
  • IO
  • bondpad
  • analog blocks

$1,200/mm2

$600/mm2

AMS 0.35 μm CMOS – High Voltage

Product Page

  • 3.3/5/50V
  • 2P4MH35B4D3kit includes:
    • standard cell
    • IO
    • bondpad

 

H35B4D3

kit includes:

  • standard cell
  • IO
  • bondpad

$1,320/mm2

$600/mm2

Open-Gate Silicon JFET

Product Page

  • JFET with unpassivated gate, enabling user-deposition of sensor material
  • 1 metal routing layer
  • silicon substrate

Silicon Photonics General-Purpose

Product Page

  • SOI, 220 nm top Si, 2000 nm BOX
  • 193 nm lithography for waveguides
  • 6 implants for optical modulators
  • Ge deposition & implanting for photodetectors
  • Two metal levels for routing plus metal heater

$14,000

(Per 3 x 8 mm2 design)

$4,300

(Per 3 x 8 mm2 design)

III-V Epitaxy on GaAs Substrates, InP and Ge Substrates

Product Page

Features – Provide III – V materials to fabricate

  • Lasers, LEDs and SOAs on InP substrate
  • VCSELs, nonlinear optics and high mobility devices on GaAs substrate
  • Multi-junction solar cells and converters on Ge substrate
  • Other applications

 

Design Kit: CPFC Optoelectronic/Photonic III-V Process

Epi-Structure Form

MEMSCAP PiezoMUMPs

Product Page

  • SOI MEMS
  • 25um structure layer
  • piezoelectric metal

$1,420

(per 5 x 5 mm2 design) 

$550

(per 5 x 5 mm2 design) 

PolyMUMPs Multi-User MEMS Process Technology

Product Page

  • surface MEMS
  • three structure layers

$1,420

(per 5 x 5 mm2 design) 

$550

(per 5 x 5 mm2 design) 

Post-Processing for PolyMUMPs

Product Page

Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0

Design Kit: PolyMUMPs Design Handbook for MEMSPro

$860/design

$325/per design

Teledyne DALSA MIDIS Platform

Product Page

  • sealed-cavity MEMS
  • 30um structure layer
  • high-vacuum

$9,800

(per 4 x 4 mm2 design) 

$3,400

(per 4 x 4 mm2 design) 

MicraGEM-Si™ MEMS Process

Product Page

  • SOI MEMS
  • two structure layers
  • three trench depths

 

 

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

STM 28 nm CMOS FDSOI

ST Microelectronics logo

Product Page

  • 1.0/1.8V
  • 1P8M
  • no mimcap
  • LVT

RF_mmW_6U1x_2T8x_LB

kit includes:

  • standard cell
  • IO
  • bondpad

Libraries:

  • custom memory generator

$12,500/mm2

(Minimum charge is for a 1.25mm2 design)

$5,000/mm2

(Minimum charge is for a 1.25mm2 design)

TSMC 65 nm CMOS GP

Product Page

  • 1.0/2.5V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

CRN65GP

Libraries:

  • standard cell
  • IO
  • bondpad
  • memory generator

$5,200/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$2,350/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design.)

TSMC 65 nm CMOS LP

Product Page

  • 1.2/2.5V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

CRN65LP

Libraries:

  • standard cell
  • IO
  • bondpad

$5,200/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$2,350/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

TSMC 0.13 μm CMOS

Product Page

  • 1.2/3.3V
  • 1P8M
  • mimcap

 

CR013G

Libraries:

  • standard cells
  • IO
  • bondpad

$2,050/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$1,025/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

TSMC 0.18 μm CMOS


Product Page

  • 1.8/3.3V
  • 1P6M
  • mimcap
  • LVT/native/HVT

CM013G

Libraries:

  • standard cell
  • IO
  • bondpad

$1,100/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$425/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

TSMC 0.35 μm CMOS

Product Page

  • 3.3/5V
  • 2P4M

$475/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

$250/mm2

(Minimum charge is for a 1.1 x 1.1 mm2 design)

AMS 0.35 μm CMOS – Basic

Product Page

  • 3.3/5V
  • 2P4M

C35B4C3

kit includes:

  • standard cell
  • IO
  • bondpad
  • analog blocks

$1,200/mm2

$600/mm2

AMS 0.35 μm CMOS – Opto

Product Page

  • 3.3/5V
  • 2P4M
  • anti-reflective coating

C35B4O1

kit includes:

  • standard cell
  • IO
  • bondpad
  • analog blocks

$1,200/mm2

$600/mm2

AMS 0.35 μm CMOS – High Voltage

Product Page

  • 3.3/5/50V
  • 2P4MH35B4D3kit includes:
    • standard cell
    • IO
    • bondpad

 

H35B4D3

kit includes:

  • standard cell
  • IO
  • bondpad

$1,320/mm2

$600/mm2

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

Silicon Photonics General-Purpose

Product Page

  • SOI, 220 nm top Si, 2000 nm BOX
  • 193 nm lithography for waveguides
  • 6 implants for optical modulators
  • Ge deposition & implanting for photodetectors
  • Two metal levels for routing plus metal heater

$14,000

(Per 3 x 8 mm2 design)

$4,300

(Per 3 x 8 mm2 design)

III-V Epitaxy on GaAs Substrates, InP and Ge Substrates

Product Page

Features – Provide III – V materials to fabricate

  • Lasers, LEDs and SOAs on InP substrate
  • VCSELs, nonlinear optics and high mobility devices on GaAs substrate
  • Multi-junction solar cells and converters on Ge substrate
  • Other applications

 

Design Kit: CPFC Optoelectronic/Photonic III-V Process

Epi-Structure Form

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

Post-Processing for PolyMUMPs

Product Page

Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0

Design Kit: PolyMUMPs Design Handbook for MEMSPro

$860/design

$325/per design

MEMSCAP PiezoMUMPs

Product Page

  • SOI MEMS
  • 25um structure layer
  • piezoelectric metal

$1,420

(per 5 x 5 mm2 design) 

$550

(per 5 x 5 mm2 design) 

PolyMUMPs Multi-User MEMS Process Technology

Product Page

  • surface MEMS
  • three structure layers

$1,420

(per 5 x 5 mm2 design) 

$550

(per 5 x 5 mm2 design) 

Teledyne DALSA MIDIS Platform

Product Page

  • sealed-cavity MEMS
  • 30um structure layer
  • high-vacuum

$9,800

(per 4 x 4 mm2 design) 

$3,400

(per 4 x 4 mm2 design) 

MicraGEM-Si™ MEMS Process

Product Page

  • SOI MEMS
  • two structure layers
  • three trench depths

 

 

Process NameFeaturesDesign KitCanadian AcademicCanadian Academic Peer ReviewedList

Open-Gate Silicon JFET

Product Page

  • JFET with unpassivated gate, enabling user-deposition of sensor material
  • 1 metal routing layer
  • silicon substrate

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