FAB

Available Technologies

Through supplier partnerships, we offer multi-project wafer services and related fabrication services in a variety of technologies. View our fabrication schedule online.

All prototyping technologies remain open for international academic research and industrial R&D.
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Eligibility reviewed pricing is limited to one design block or the mm² specified.

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Features	Design Kits and Libraries	List Price (USD)*	Post_tag	Title
SOI, 220 nm top Si, 3000 nm BOX 193 nm lithography for waveguides Silicon nitride integration 6 implants for optical modulators Ge deposition & implanting for photodetectors Two metal levels for routing plus metal heater	Design Kit: Siemens L-Edit Photonics for the Advanced Micro Foundry (AMF) Silicon Photonics Fabrication Process Design Kit: Luceda-Tanner-AMF Silicon Photonics Design Platform Design Kit: Siemens Pyxis for the Advanced Micro Foundry (AMF) Silicon Photonics Fabrication Process	$917/mm² (Minimum charge is for a 24 mm² design)	AMF Silicon Photonics, industry, Photonics, Photonics Featured	AMF Silicon Photonics General-Purpose Fabrication Process
3.3 V/5 V 2P4M	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$998/mm² (Minimum charge is for a 10 mm² design)	AMS, industry, microelectronics	AMS 0.35 µm CMOS Process Technology (Basic)
3.3 V/5 V/50 V 2P4MH35B4D3 kit includes: standard cell IO bondpad	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,372/mm² (Minimum charge is for a 10 mm² design)	AMS, industry, microelectronics, Microelectronics Featured	AMS 0.35 µm CMOS Process Technology (High-Voltage)
3.3 V/5 V 2P4M anti-reflective coating	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1247/mm² (Minimum charge is for a 20 mm² design)	AMS, industry, microelectronics	AMS 0.35 µm CMOS Process Technology (Opto)
SOI, 220 nm top Si, 2000 nm BOX 100 keV electron-beam lithography for waveguides One metal level for routing plus metal heater Future options include implants for optical modulators Note: Every individual accessing this technology is required to read and sign a technology-specific NDA. If you have not done so, please contact Dr. Susan Xu as soon as possible to get started.	Design Kit: Siemens L-Edit Photonics for the Applied Nanotools Silicon Photonics Fabrication Process	Contact fab@cmc.ca.	industry, Photonics, Photonics Featured	Applied Nanotools (ANT) NanoSOI Fabrication Process
SiN, 400 nm on 4.5 µm oxide box layer 100 keV electron-beam lithography for waveguides One metal level for routing plus metal heater	Design Kit: Siemens L-Edit Photonics for Applied Nanotools (ANT) Photonics Silicon Nitride (SiN) Fabrication Process	Contact fab@cmc.ca.	industry, Photonics, Photonics Featured	Applied Nanotools (ANT) Silicon Nitride (SiN) Fabrication Process
Molecular Beam Epitaxy (MBE) Gas-Source MBE Metal-Organic Chemical Vapor Deposition (MOCVD)	See the Opto Epitaxy Form.	Contact fab@cmc.ca.	Photonics	Compound Semiconductor Epitaxy
Silicon junction field effect transistors with unpassivated gate, enabling user-deposition of sensor material One metal routing layer, silicon substrate Up to 10 copies per design (10 x 10 mm). Available as bare die or packaged parts Sub dicing into 5 x 5 mm² dies is available for an additional cost.	Design Kit: Electronic Sensor Platform (ESP) in L-Edit and Synopsys Sentaurus	$80.00/mm² (Minimum charge is for a 5 mm x 5 mm design) $41.30/mm² (Minimum charge is for a 10 mm x 10 mm design)	3IT, Emerging, Experimental, MNI, MNI Featured	Electronic Sensor Platform (ESP)
Logic Voltages → Vnom: 0.8V, Vmax: 0.945V 4 VTs: SLVT / LVT / RVT / HVT IO offering: 1.2 V, 1.35 V, 1.5 V and 1.8 V EG Devices Well resistor, precision MOL resistor, MIM / MIM4 / APMOM / MOS / VNCAP capacitors, ESD, eFuse, VPNP, VNPN and Diodes, Inductors, Transmission line Interlevel Low-K and Ultralow-K dielectrics Packaging options: C4 solder, Round or Oblong Copper Pillar Bump, Micro pillar Bump	GF12lp0_4.0 Device library RF library ESD library	$44,850/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $35,880/mm² (Minimum charge is for a 9 mm² design)	GLOBALFOUNDRIES, microelectronics, Microelectronics Featured	GlobalFoundries^® 12 LP
0.4 V to 0.8 V nominal core voltage 1.2 V / 1.5 V / 1.8 V IO options Four core device Vt’s (FBB, RBB & eLVT) RF BEOL /w ultra thick metal stacks APMOM capacitor	GF22FDX-EXT	$27,233/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $21,786/mm² (Minimum charge is for a 9 mm² design)	GLOBALFOUNDRIES, industry, microelectronics	GlobalFoundries^® 22FDX FDSOI 22 nm
1 V/1.5 V/1.8 V 1P8M process Native/HVT/SVT/UVT FETs N+ silicide resistor Vertical natural capacitor BEOL inductors Thin oxide Varactor ft/fmax 290/410 GHz	45RFSOI-RF V1.2_0.2	$15,249.00/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $12,199.00/mm² (Minimum charge is for a 12 mm² design)	GLOBALFOUNDRIES, microelectronics	GlobalFoundries^® 45 nm RFSOI
1.2 V/1.8 V/2.5 V/3.3 V 1P10M process Native/HVT FETs ft/fmax 310/370GHz Twin_ or triple_well (NFET in isolated pwell) CMOS technology MIM/Dual/high Q MIM capcitors Series/Parallel spirals Inductors PIN / Schottky Barrier diode	90HPSIGE-9HP V1.3_0.0	$10,764/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $8,611/mm² (Minimum charge is for a 12 mm² design)	GLOBALFOUNDRIES, industry, microelectronics	GlobalFoundries^® 90 nm BiCMOS SiGe 9HP
1.2 V/2.5 V Core voltage 2.5 V/3.3 V IO voltage 5 metal base stack, with option to 8 levels of metallization High performance enhanced FET Ft/fmax 250/340 GHz MIM and Dual MIM Regular Vt and Triple well FET options Series/Parallel spirals Inductors µm/mm wave passive components Thin/Thick dual gate oxide		$7,176/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $5,741/mm² (Minimum charge is for a 12 mm² design)	GLOBALFOUNDRIES, industry, microelectronics	GlobalFoundries^® SiGe 8XP BiCMOS 130 nm
Monolithic integration of RF, analog and SiPh (45 nm SOI CMOS technology) Minimum lithographic image of 40 nm (gate only) Core Voltages: 0.9V, 1V Ge EPI integration coupled into SOI WG BEOL Metallization Stacks – 9 levels Far-BEOL V-groove integration for fibre attach Photonic element library Electronic element library	45SPCLO_v1.0_1.0a, includes: Photonic element library (Polarization splitter & rotator, modulators, detectors Phase shifter, WGs, edge coupler, grating coupler, etc.) Electronic element library (FETs, precision resistors, capacitor, inductors, photo diode, ESD, etc.)	$15,249/mm² (Minimum charge is for a 2.455 mm x 5 mm design) Note: This price is available only to academic researchers. $12,199/mm² (Minimum charge is for a 5 mm x 5 mm design)	GLOBALFOUNDRIES, Photonics, Photonics Featured, silicon photonics	GlobalFoundries^® Silicon Photonics - GF Fotonix™ (45SPCLO)
SOI substrate Far-BEOL V-groove for fibre attach 1P7M LVT	90SIPH-9WG, includes: photonic element library electronic element library bondpad	Dedicated runs only. Contact fab@cmc.ca.	GLOBALFOUNDRIES, Photonics, Photonics Featured, silicon photonics	GlobalFoundries^® Silicon Photonics 9WG
Other GlobalFoundries technologies are available. Please contact fab@cmc.ca if there is a technology you are interested in and would like a quote.		Contact fab@cmc.ca.	GLOBALFOUNDRIES, Photonics	GlobalFoundries^® Technologies – Others Available
SOI MEMS 10 μm structure layer piezoelectric metal	Design Kit: PiezoMUMPs for Coventorware Design Kit: MEMSCAP PiezoMUMPs Design Handbook	$6,889 /mm² (Minimum charge is for a 4.3 mm x 4.3 mm design)	industry, MEMS, MEMSCAP	MEMSCAP PiezoMUMPs Process Technology
Surface MEMS Three structure layers	Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0 Design Kit: PolyMUMPs Design Handbook for MEMSPro Design Kit: PolyMUMPs MEMS Process for CoventorWare	$7,750/mm² (Minimum charge is for a 4.75 x 4.75 mm² design)	industry, MEMS, MEMSCAP, MNI Featured	MEMSCAP PolyMUMPs Multi-User MEMS Process Technology
Optional HF release and supercritical carbon dioxide drying. Allows users to develop acoustics, motion sensors, optical MEMS, etc.	Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0 Design Kit: PolyMUMPs Design Handbook for MEMSPro	$3,301/mm² (Minimum charge is for a 4.75 x 4.75 mm² design)	MEMS, MEMSCAP, MNI Featured	MEMSCAP Post-Processing for PolyMUMPs
1.0 V/1.8 V 1P8M no mimcap LVT	Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm CMOS – CMOS28LP Design Methodology: ST 28 nm FD-SOI CMOS Technology – Analog Design Flow and Reference Design Design Methodology: STMicroelectronics 28nm FD-SOI CMOS Technology Digital/Mixed-Mode Design Flow	$14,030/mm² (Minimum charge is for a 1.25 mm² design)	microelectronics, Microelectronics Featured, STM	STM 28nm FD SOI CMOS
Getter-free high-vacuum sealing allows resonator Q factors > 20,000 Efficient wafer-level packaging minimizes overall die size 1.5-μm feature size in a 30-μm thick membrane Comb height control allows out-of-plane sensing TSV allows compact design ready for co-packaging Deliver 40 copies for each design Sealed-cavity MEMS 30-μm structure layer High-vacuum	Teledyne DALSA MIDIS Design Kits	Contact fab@cmc.ca.	industry, MEMS, Teledyne	Teledyne DALSA MIDIS Platform
Two thick SOI structure layers with up to three functional levels of silicon thickness option. This enables structures such as vertical comb-drive actuators. Base and top device layers are electrically connected through the bond interface, allowing 3D routing of electrical signals. Patterned low-stress gold metallization on the top surface is suited for highly reflective mirrors and contact pads for gold wire bonding. Design size 4 mm x 4 mm SOI MEMS Two structure layers Three trench depths	Design Kit: Micralyne MicraGEM-Si™, for Tanner L-Edit Design Handbook: Micralyne MicraGEM-Si™ (ICI-319)	Dedicated runs only. Contact fab@cmc.ca.	MEMS, Teledyne	Teledyne Micralyne Micralyne MicraGEM-Si™ MEMS Process
1.2 V/3.3 V 1P8M mimcap	Design Kit: TSMC 0.13 µm CMOS	$2,583/mm² (Minimum charge is for a 25 mm² design)	microelectronics, TSMC	TSMC 0.13 µm CMOS RF Mixed-Signal Process
1.8 V/3.3 V 1P6M mimcap LVT/native/HVT	Design Kit: TSMC 0.18µm CMOS Process Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Library: ARM Digital Standard Cell and IO Libraries for TSMC 0.18 µm CMOS Design Library: TSMC 0.18 µm CMOS Standard Cells Library – tsmc-cl018g_sc-x_2004q3v1 Design Flow: Digital IC Design (from RMC)	$1,794/mm² (Minimum charge is for a 5 mm² design)	microelectronics, TSMC	TSMC 0.18 µm CMOS Process Technology
3.3 V/5 V 2P4M	Design Kit: TSMC 0.35-micron CMOS-CM0SP35 Design Kit: TSMC 0.35 µm CMOS Process Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$540/mm² (Minimum charge is for a 25 mm² design)	microelectronics, TSMC	TSMC 0.35 µm CMOS Process Technology
0.9 V (core)/1.8 V (I/O) 1P9M (1P9M_6x1z1u) High K – Metal gate	Standard cell	$19,806/mm²	microelectronics, Microelectronics Featured, TSMC	TSMC 28 nm CMOS Process Technology (HPC+RF)
1.0 V/2.5 V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 Design Kit: TSMC 65 nm CMOS GP – CRN65GP	$8,324/mm²	microelectronics, TSMC	TSMC 65 nm GP CMOS Process Technology
1.2 V/2.5 V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Kit: TSMC 65 nm CMOS GP – CRN65LP Design Library: TSMC 65 nm LP Standard Cell Libraries – tcbn65lp Design Library: TSMC 65 nm LP IO Digital Libraries – tpdn65lpnv2 Design Library: TSMC 65nm LP IO Analog Libraries – tpan65lpnv2	$8,324/mm²	microelectronics, TSMC	TSMC 65 nm LP CMOS Process Technology
Nb resonators with Q-factor of approximately one million Aluminum junctions		$30,000 (per 5 x 5 mm² design)	industry, Quantum Featured, VTT	VTT Aluminum Junction Process
One tri-layer for junctions and an additional metallic layer	Design Kit: VTT Niobium SWAPS Junction Process	Contact fab@cmc.ca.	industry, Quantum Featured, VTT	VTT Niobium SWAPS Junction Process
Coming soon …				X-FAB: XT018 Automotive 180 nm BCD-on-SOI Technology Platform