FAB

Available Technologies

Through supplier partnerships, we offer multi-project wafer services and related fabrication services in a variety of technologies. View our fabrication schedule online.

  • All prototyping technologies remain open for international academic research and industrial R&D.
  • Academics in Canada are eligible for discounted pricing with Subscription. You must sign in to see it.
Process NameFeaturesDesign Kits and LibrariesList Price*
  • SOI, 220 nm top Si, 3000 nm BOX
  • 193 nm lithography for waveguides
  • Silicon nitride integration
  • 6 implants for optical modulators
  • Ge deposition & implanting for photodetectors
  • Two metal levels for routing plus metal heater

$21,000
(per 3 x 8 mm design)

AMF Silicon Photonics, industry, photonics, Photonics FeaturedAMF Silicon Photonics General-Purpose Fabrication ProcessAMF Silicon Photonics General-Purpose Fabrication Process
  • 3.3 V/5 V
  • 2P4M

$1,025/mm2

AMS, industry, microelectronicsAMS 0.35 µm CMOS Process Technology (Basic)AMS 0.35 µm CMOS Process Technology (Basic)
  • 3.3 V/5 V/50 V
  • 2P4MH35B4D3 kit includes:
    • standard cell
    • IO
    • bondpad

$1,425/mm2

AMS, industry, microelectronics, Microelectronics FeaturedAMS 0.35 µm CMOS Process Technology (High-Voltage)AMS 0.35 µm CMOS Process Technology (High-Voltage)
  • 3.3 V/5 V
  • 2P4M
  • anti-reflective coating

$1,300/mm2

AMS, industry, microelectronicsAMS 0.35 µm CMOS Process Technology (Opto)AMS 0.35 µm CMOS Process Technology (Opto)
  • SOI, 220 nm top Si, 2000 nm BOX
  • 100 keV electron-beam lithography for waveguides
  • One metal level for routing plus metal heater
  • Future options include implants for optical modulators

Note: Every individual accessing this technology is required to read and sign a technology-specific NDA. If you have not done so, please contact Dr. Susan Xu as soon as possible to get started.

Design Kit: Siemens L-Edit Photonics for the Applied Nanotools Silicon Photonics Fabrication Process

Contact fab@cmc.ca.

industry, photonics, Photonics FeaturedApplied Nanotools (ANT) NanoSOI Fabrication ProcessApplied Nanotools (ANT) NanoSOI Fabrication Process
  • SiN, 400 nm on 4.5 µm oxide box layer
  • 100 keV electron-beam lithography for waveguides
  • One metal level for routing plus metal heater

Design Kit: Siemens L-Edit Photonics for Applied Nanotools (ANT) Photonics Silicon Nitride (SiN) Fabrication Process

Contact fab@cmc.ca.

industry, photonics, Photonics FeaturedApplied Nanotools (ANT) Silicon Nitride (SiN) Fabrication ProcessApplied Nanotools (ANT) Silicon Nitride (SiN) Fabrication Process
  • Molecular Beam Epitaxy (MBE)
  • Gas-Source MBE
  • Metal-Organic Chemical Vapor Deposition (MOCVD)

See the Opto Epitaxy Form.

Contact fab@cmc.ca.

photonicsCompound Semiconductor EpitaxyCompound Semiconductor Epitaxy
  • Silicon junction field effect transistors with unpassivated gate, enabling user-deposition of sensor material
  • 1 metal routing layer, silicon substrate
  • Up to 10 copies per design (10 x 10 mm).  Available as bare die or packaged parts

Design Kit: Electronic Sensor Platform (ESP) in L-Edit and Synopsys Sentaurus

$2,600
(per 10 x 10 mm design)

3IT, Emerging, Experimental, MNI, MNI FeaturedElectronic Sensor Platform (ESP)Electronic Sensor Platform (ESP)
  • Logic Voltages → Vnom: 0.8V, Vmax: 0.945V
  • 4 VTs: SLVT / LVT / RVT / HVT
  • IO offering: 1.2 V, 1.35 V, 1.5 V and 1.8 V EG Devices
  • Well resistor, precision MOL resistor, MIM / MIM4 / APMOM / MOS / VNCAP capacitors, ESD, eFuse, VPNP, VNPN and Diodes, Inductors, Transmission line
  • Interlevel Low-K and Ultralow-K dielectrics
  • Packaging options: C4 solder, Round or Oblong Copper Pillar Bump, Micro pillar Bump
  • GF12lp0_4.0
  • Device library
  • RF library
  • ESD library

$51,525/mm2

GLOBALFOUNDRIES, microelectronics, Microelectronics FeaturedGlobalFoundries<sup>®</sup> 12 LPGlobalFoundries® 12 LP
  • 0.4 V to 0.8 V nominal core voltage
  • 1.2 V / 1.5 V / 1.8 V IO options
  • Four core device Vt’s (FBB, RBB & eLVT)
  • RF BEOL /w ultra thick metal stacks
  • APMOM capacitor
  • GF22FDX-EXT

$31,300/mm2

GLOBALFOUNDRIES, industry, microelectronicsGlobalFoundries<sup>®</sup> 22FDX FDSOI 22 nmGlobalFoundries® 22FDX FDSOI 22 nm
  • 1 V/1.5 V/1.8 V
  • 1P8M process
  • Native/HVT/SVT/UVT FETs
  • N+ silicide resistor
  • Vertical natural capacitor
  • BEOL inductors
  • Thin oxide Varactor
  • ft/fmax 290/410 GHz
  • 45RFSOI-RF V1.2_0.2

$16,600/mm2

GLOBALFOUNDRIES, industry, microelectronicsGlobalFoundries<sup>®</sup> 45 nm RFSOIGlobalFoundries® 45 nm RFSOI
  • 1.2 V/1.8 V/2.5 V/3.3 V 
  • 1P10M process 
  • Native/HVT FETs 
  • ft/fmax 310/370GHz 
  • Twin_ or triple_well (NFET in isolated pwell) CMOS technology 
  • MIM/Dual/high Q MIM capcitors 
  • Series/Parallel spirals Inductors 
  • PIN / Schottky Barrier diode 
  • 90HPSIGE-9HP  V1.3_0.0

$12,350/mm2

GLOBALFOUNDRIES, industry, microelectronicsGlobalFoundries<sup>®</sup> 90 nm BiCMOS SiGe 9HPGlobalFoundries® 90 nm BiCMOS SiGe 9HP
  • 1.2 V/2.5 V Core voltage
  • 2.5 V/3.3 V IO voltage
  • 5 metal base stack, with option to 8 levels of metallization
  • High performance enhanced FET
  • Ft/fmax 250/340 GHz
  • MIM and Dual MIM
  • Regular Vt and Triple well FET options
  • Series/Parallel spirals Inductors
  • µm/mm wave passive components
  • Thin/Thick dual gate oxide

$8,125/mm2

GLOBALFOUNDRIES, industry, microelectronicsGlobalFoundries<sup>®</sup> SiGe 8XP BiCMOS 130 nmGlobalFoundries® SiGe 8XP BiCMOS 130 nm
  • Monolithic integration of RF, analog and SiPh (45 nm SOI CMOS technology)
  • Minimum lithographic image of 40 nm (gate only)
  • Core Voltages: 0.9V, 1V
  • Ge EPI integration coupled into SOI WG
  • BEOL Metallization Stacks – 9 levels
  • Far-BEOL V-groove integration for fibre attach
  • Photonic element library
  • Electronic element library

45SPCLO_v1.0_1.0a, includes:

  • Photonic element library (Polarization splitter & rotator, modulators, detectors
    Phase shifter, WGs, edge coupler, grating coupler, etc.)
  • Electronic element library (FETs, precision resistors, capacitor, inductors, photo diode, ESD, etc.)

Contact fab@cmc.ca.

GLOBALFOUNDRIES, photonics, Photonics Featured, silicon photonicsGlobalFoundries<sup>®</sup> Silicon Photonics <strong>45SPCLO</strong>GlobalFoundries® Silicon Photonics 45SPCLO
  • SOI substrate
  • Far-BEOL V-groove for fibre attach
  • 1P7M
  • LVT

90SIPH-9WG, includes:

  • photonic element library
  • electronic element library
  • bondpad

Dedicated runs only. Contact fab@cmc.ca.

GLOBALFOUNDRIES, photonics, Photonics Featured, silicon photonicsGlobalFoundries<sup>®</sup> Silicon Photonics 9WGGlobalFoundries® Silicon Photonics 9WG

Other GF® technologies are available. Please contact fab@cmc.ca if there is a technology you are interested in and would like a quote. 

Please contact fab@cmc.ca.

GlobalFoundries<sup>®</sup> Technologies – Others AvailableGlobalFoundries® Technologies – Others Available
  • SOI MEMS
  • 25um structure layer
  • piezoelectric metal

$2,200
(per 4.3 x 4.3 mm design) 

industry, MEMS, MEMSCAPMEMSCAP PiezoMUMPs Process TechnologyMEMSCAP PiezoMUMPs Process Technology
  • Surface MEMS
  • Three structure layers

$2,000
(per 4.75 x 4.75 mm design) 

industry, MEMS, MEMSCAP, MNI FeaturedMEMSCAP PolyMUMPs Multi-User MEMS Process TechnologyMEMSCAP PolyMUMPs Multi-User MEMS Process Technology
  • Optional HF release and supercritical carbon dioxide drying.
  • Allows users to develop acoustics, motion sensors, optical MEMS, etc.

$750
(per 4.75 x 4.75 mm design)

MEMS, MEMSCAP, MNI FeaturedMEMSCAP Post-Processing for PolyMUMPsMEMSCAP Post-Processing for PolyMUMPs
  • 1.0 V/1.8 V
  • 1P8M
  • no mimcap
  • LVT

$16,075
(Minimum charge is for a 1.25 mm2 design)

microelectronics, Microelectronics Featured, STMSTM 28nm FD SOI CMOSSTM 28nm FD SOI CMOS
  • Getter-free high-vacuum sealing allows resonator Q factors > 20,000
  • Efficient wafer-level packaging minimizes overall die size
  • 1.5-μm feature size in a 30-μm thick membrane
  • Comb height control allows out-of-plane sensing
  • TSV allows compact design ready for co-packaging
  • Deliver 40 copies for each design
  • Sealed-cavity MEMS
  • 30-μm structure layer
  • High-vacuum

$10,550
(per 4 x 4 mm2 design) 

industry, MEMS, TeledyneTeledyne DALSA MIDIS PlatformTeledyne DALSA MIDIS Platform
  • Two thick SOI structure layers with up to three functional levels of silicon thickness option. This enables structures such as vertical comb-drive actuators.
  • Base and top device layers are electrically connected through the bond interface, allowing 3D routing of electrical signals.
  • Patterned low-stress gold metallization on the top surface is suited for highly reflective mirrors and contact pads for gold wire bonding.
  • Design size 4 mm x 4 mm
  • SOI MEMS
  • Two structure layers
  • Three trench depths

Dedicated runs only. Contact fab@cmc.ca.

MEMS, TeledyneTeledyne Micralyne Micralyne MicraGEM-Si™ MEMS ProcessTeledyne Micralyne Micralyne MicraGEM-Si™ MEMS Process
  • 1.2 V/3.3 V
  • 1P8M
  • mimcap

$2,800/mm2

microelectronics, TSMCTSMC 0.13 µm CMOS RF Mixed-Signal ProcessTSMC 0.13 µm CMOS RF Mixed-Signal Process
  • 1.8 V/3.3 V
  • 1P6M
  • mimcap
  • LVT/native/HVT

$1,475/mm2

microelectronics, TSMCTSMC 0.18 µm CMOS Process TechnologyTSMC 0.18 µm CMOS Process Technology
  • 3.3 V/5 V
  • 2P4M

$550
(Minimum charge is for a 12 mm2 design)

microelectronics, TSMCTSMC 0.35 µm CMOS Process TechnologyTSMC 0.35 µm CMOS Process Technology
  • 0.9 V (core)/1.8 V (I/O)
  • 1P9M (1P9M_6x1z1u)
  • High K – Metal gate
  • Standard cell

$16,750/mm2

microelectronics, Microelectronics Featured, TSMCTSMC 28 nm CMOS Process Technology (HPC+RF)TSMC 28 nm CMOS Process Technology (HPC+RF)
  • 1.0 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

$7,350/mm2

microelectronics, TSMCTSMC 65 nm GP CMOS Process TechnologyTSMC 65 nm GP CMOS Process Technology
  • 1.2 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT
  • Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v
  • Design Kit: TSMC 65 nm CMOS GP – CRN65LP
  • Design Library: TSMC 65 nm LP Standard Cell Libraries – tcbn65lp
  • Design Library: TSMC 65 nm LP IO Digital Libraries – tpdn65lpnv2
  • Design Library: TSMC 65nm LP IO Analog Libraries – tpan65lpnv2

$7,350/mm2

microelectronics, TSMCTSMC 65 nm LP CMOS Process TechnologyTSMC 65 nm LP CMOS Process Technology

One tri-layer for junctions and an additional metallic layer

$7,375
(per 5 x 5 mm design)

industry, photonics, Photonics FeaturedVTT Niobium SWAPS Junction ProcessVTT Niobium SWAPS Junction Process

Coming soon …

X-FAB: XT018 Automotive 180 nm BCD-on-SOI Technology PlatformX-FAB: XT018 Automotive 180 nm BCD-on-SOI Technology Platform

The CMC SponsorChip program helps companies enhance their research efforts and links to academic researchers.

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