FAB Technologies

Available Technologies

Through supplier partnerships, we offer multi-project wafer services and related fabrication services in a variety of technologies. View our fabrication schedule online.

All prototyping technologies remain open for international academic research and industrial R&D.
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Features	Design Kits and Libraries	List Price (USD)*	Post_tag	Title	Note
Silicon junction field effect transistors (JFETs) with unpassivated gate, enabling user-deposition of sensor material Current modulation with top gate Up to 10 copies per design (10 mm x 10 mm) Available as bare or packaged dies Sub-dicing into 5 mm x 5 mm dies is available for an additional cost	Design Kit: Electronic Sensor Platform (ESP)	$2,000 (per 5 mm x 5 mm design) $4,130 (per 10 mm x 10 mm design)	3IT, Emerging, Experimental, MNI, MNI Featured	3iT Electronic Sensor Platform (ESP)
Al-Al-ALOx-AL Manhattan junctions (30-x-60 nm) thickness Current density around 2 uA/um² Sapphire substrate Nb layer 100 nm with a 4 ohm/square resistivity and a 0.6 pH/square kinetic inductance Resonators with Q-factor of approx. 1 million T1 and T2 of qubits from test runs of 35 us 5 x 5 mm design space	Design kit: 3iT Superconducting quantum Al_JJ_Nb (SupraFab)	$5,060 (per 5 mm x 5 mm design)	3IT, Emerging, Experimental, MNI, MNI Featured	3iT Superconducting Quantum Al_JJ_Nb Two-layer Process
SOI, 220 nm top Si, 3000 nm BOX 193 nm lithography for waveguides Silicon nitride integration 6 implants for optical modulators Ge deposition & implanting for photodetectors Two metal levels for routing plus metal heater	Design Kit: Siemens L-Edit Photonics for the Advanced Micro Foundry (AMF) Silicon Photonics Fabrication Process Design Kit: Luceda-Tanner-AMF Silicon Photonics Design Platform Design Kit: Siemens Pyxis for the Advanced Micro Foundry (AMF) Silicon Photonics Fabrication Process	$22,000 (per 7.4 mm x 3 mm design)	AMF Silicon Photonics, industry, Photonics, Photonics Featured, Quantum	AMF Silicon Photonics General-Purpose Fabrication Process
Advanced high-speed Modulators and Ge Photodetectors designed for ultra-fast data transmission in O and C bands. Non-Suspended Edge Coupler, a critical innovation for precise passive alignment. Access to LPCVD Silicon Nitride technology for improved material properties and performance.		$22,000 (per 7.4 mm x 3 mm design)	AMF Silicon Photonics, industry, Photonics, Photonics Featured, Quantum	AMF Silicon Photonics High-Performance Fabrication Process	May 4, 2026: Created by Yuquan per CPR-1177.
standard cell IO bondpad	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$998/mm² (Minimum charge is for a 10 mm² design)	AMS, industry, Microelectronics	AMS 0.35 µm CMOS Process Technology (Basic)
3.3 V/5 V/50 V 2P4MH35B4D3 kit includes: standard cell IO bondpad	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,372/mm² (Minimum charge is for a 10 mm² design)	AMS, industry, Microelectronics, Microelectronics Featured	AMS 0.35 µm CMOS Process Technology (High-Voltage)
3.3 V/5 V 2P4M anti-reflective coating	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1247/mm² (Minimum charge is for a 20 mm² design)	AMS, industry, Microelectronics	AMS 0.35 µm CMOS Process Technology (Opto)
SOI, 220 nm top Si, 2000 nm BOX 100 keV electron-beam lithography for waveguides One metal level for routing plus metal heater Future options include implants for optical modulators Note: Every individual accessing this technology is required to read and sign a technology-specific NDA. If you have not done so, please contact Dr. Susan Xu as soon as possible to get started.	Design Kit: Siemens L-Edit Photonics for the Applied Nanotools Silicon Photonics Fabrication Process	Contact [email protected].	industry, Photonics, Photonics Featured	Applied Nanotools (ANT) NanoSOI Fabrication Process
SiN, 400 nm on 4.5 µm oxide box layer 100 keV electron-beam lithography for waveguides One metal level for routing plus metal heater	Design Kit: Siemens L-Edit Photonics for Applied Nanotools (ANT) Photonics Silicon Nitride (SiN) Fabrication Process	Contact [email protected].	industry, Photonics, Photonics Featured, Quantum	Applied Nanotools (ANT) Silicon Nitride (SiN) Fabrication Process
Molecular Beam Epitaxy (MBE) Gas-Source MBE Metal-Organic Chemical Vapor Deposition (MOCVD)	See the Opto Epitaxy Form.	Contact [email protected].	Photonics	Compound Semiconductor Epitaxy
Logic Voltages → Vnom: 0.8V, Vmax: 0.945V 4 VTs: SLVT / LVT / RVT / HVT IO offering: 1.2 V, 1.35 V, 1.5 V and 1.8 V EG Devices Well resistor, precision MOL resistor, MIM / MIM4 / APMOM / MOS / VNCAP capacitors, ESD, eFuse, VPNP, VNPN and Diodes, Inductors, Transmission line Interlevel Low-K and Ultralow-K dielectrics Packaging options: C4 solder, Round or Oblong Copper Pillar Bump, Micro pillar Bump	PDK version: V1.0_7.0b Device library RF library ESD library This technology node offers a wide range of IPs, including standard-cell libraries with different threshold voltages, IO libraries, power-management libraries, memories, and more. You may obtain the libraries directly from the vendors (ARM, Synopsys, GLOBAL FOUNDRIES).	$37,050/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $29,952/mm² (Minimum charge is for a 4 mm² design)	GLOBALFOUNDRIES, Microelectronics, Microelectronics Featured	GlobalFoundries® 12 LP
0.4 V to 0.8 V nominal core voltage 1.2 V / 1.5 V / 1.8 V /3.3 V IO options Four core device Vt’s SLVT, LVT, RVT, and HVT Body bias settings (RBB, FBB, ZBB) and adaptive body biasing RF BEOL /w ultra thick metal stacks APMOM capacitor	PDK version: V1.0_4.1 Device library RF library ESD library This technology node offers a wide range of IPs, including standard cell libraries with different threshold voltages, IO libraries, body-biasing libraries, and memories. Libraries are to be obtained directly from the vendors (ARM, Synopsys, GLOBAL FOUNDRIES).	$24,075/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $17,997/mm² (Minimum charge is for a 4 mm² design)	GLOBALFOUNDRIES, industry, Microelectronics	GlobalFoundries® 22FDX FDSOI 22 nm
Vnom: 1V, 0.8V (ULP) IO offering: 1.5V, 1.8V (EG) and1.8V, 2.5V, 3.3V (ZG) UHVT NFET and PFET devices with ultra low leakage Zero-Vt NFET devices Shallow trench isolation (STI) LDFET Transistors Vertical PNP bipolar transistor Well resistor, NCAP/PCAP/VNCAP/APMOM, UTM30x Inductor, ESD, eFuse Passivation and interlevel low-k and ultralow-k dielectrics Packaging options: WB pads, C4 solder, Cu Pillar terminals	28SLPe V1.0_7.0a	$17,238/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $12,093/mm² (Minimum charge is for a 4 mm² design)	GLOBALFOUNDRIES, Microelectronics, Photonics, Photonics Featured, silicon photonics	GlobalFoundries® 28 SLPe
1 V/1.5 V/1.8 V 1P8M process Native/HVT/SVT/UVT FETs N+ silicide resistor Vertical natural capacitor BEOL inductors Thin oxide Varactor ft/fmax 290/410 GHz	45RFSOI-RF V1.2_0.2	$12,486/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $10,166/mm² (Minimum charge is for a 12 mm² design)	GLOBALFOUNDRIES, Microelectronics	GlobalFoundries® 45 nm RFSOI
5V CMOS 8/10/12V Isolated Low Rdson EDMOS MIM/APMOM, Inductor, ESD Packaging options: WB pads, C4 solder	55BCDlite V1.0_13.0a	$7,774/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $5,406/mm² (Minimum charge is for a 9 mm² design)	GLOBALFOUNDRIES, Photonics, Photonics Featured, silicon photonics	GlobalFoundries® 55 nm BCDLite
1.2 V/1.8 V/2.5 V/3.3 V 1P10M process Native/HVT FETs ft/fmax 310/370GHz Twin_ or triple_well (NFET in isolated pwell) CMOS technology MIM/Dual/high Q MIM capcitors Series/Parallel spirals Inductors PIN / Schottky Barrier diode	90HPSIGE-9HP V1.3_0.0	$10,140/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $7,051/mm² (Minimum charge is for a 12 mm² design)	GLOBALFOUNDRIES, industry, Microelectronics	GlobalFoundries® 90 nm BiCMOS SiGe 9HP
1.2 V/2.5 V Core voltage 2.5 V/3.3 V IO voltage 5 metal base stack, with option to 8 levels of metallization High performance enhanced FET Ft/fmax 250/340 GHz MIM and Dual MIM Regular Vt and Triple well FET options Series/Parallel spirals Inductors µm/mm wave passive components Thin/Thick dual gate oxide		$6,760/mm² (Minimum charge is for a 1 mm² design) Note: This price is available only to academic researchers. $4,700/mm² (Minimum charge is for a 12 mm² design)	GLOBALFOUNDRIES, industry, Microelectronics	GlobalFoundries® SiGe 8XP BiCMOS 130 nm
Monolithic integration of RF, analog and SiPh (45 nm SOI CMOS technology) Minimum lithographic image of 40 nm (gate only) Core Voltages: 0.9V, 1V Ge EPI integration coupled into SOI WG BEOL Metallization Stacks – 9 levels Far-BEOL V-groove integration for fibre attach Photonic element library Electronic element library	45SPCLO_v1.0_1.0a, includes: Photonic element library (Polarization splitter & rotator, modulators, detectors Phase shifter, WGs, edge coupler, grating coupler, etc.) Electronic element library (FETs, precision resistors, capacitor, inductors, photo diode, ESD, etc.)	$161,476 (per 2.455 mm x 5 mm design) Note: This price is available only to academic researchers. $256,360 (per 5 mm x 5 mm design)	GLOBALFOUNDRIES, Photonics, Photonics Featured, silicon photonics	GlobalFoundries® Silicon Photonics - GF Fotonix™ (45SPCLO)
SOI substrate Far-BEOL V-groove for fibre attach 1P7M LVT	90SIPH-9WG, includes: photonic element library electronic element library bondpad	Dedicated runs only. Contact [email protected].	GLOBALFOUNDRIES, Photonics, Photonics Featured, silicon photonics	GlobalFoundries® Silicon Photonics 9WG
Other GlobalFoundries technologies are available. Please contact [email protected] if there is a technology you are interested in and would like a quote.		Contact [email protected].	GLOBALFOUNDRIES, Photonics	GlobalFoundries® Technologies – Others Available
Ceramic packaging and interposers Low-loss RF, microwave, and mm-wave circuits Compact passive structures and lumped-element networks Thermal management through metallized vias High-density interconnect substrates for wire-bond or flip-chip assembly Research and prototyping designs that benefit from a standardized LTCC stack and rule deck	Design Kit: LTCC PDK for LTCC A6M Shared Run	For shared-run participation, tile options, and pricing details, contact [email protected].		LTCC A6M Shared Run at ÉTS	Prototyping and low volume production capabilities in multilayer ceramics
SOI MEMS 10 μm structure layer piezoelectric metal	Design Kit: Piezo MEMS for Coventorware Design Kit: Science Foundry Piezo MEMS Design Handbook	Coming soon …	industry, MEMS, Science Foundry	Science Foundry Piezo MEMS Process Technology	$1,955 (per 4.75 mm x 4.75 mm design) $7,822 (per 10 mm x 10 mm design)
Surface MEMS Three structure layers	Design Kit: Poly MEMS Design Handbook for MEMSPro Design Kit: Poly MEMS Process for CoventorWare	Coming soon …	industry, MEMS, MNI Featured, Science Foundry	Science Foundry Poly MEMS Multi-User MEMS Process Technology	$1,740 (per 4.75 mm x 4.75 mm design) $6,961 (per 10 mm x 10 mm design)
Optional HF release and supercritical carbon dioxide drying. Allows users to develop acoustics, motion sensors, optical MEMS, etc.	Design Kit: Poly MEMS Design Handbook for MEMSPro	Coming soon …	MEMS, MNI Featured, Science Foundry	Science Foundry Post-Processing for Poly MEMS	$825 (per 4.75 mm x 4.75 mm design) $3,301 (per 10 mm x 10 mm design)
1.0 V/1.8 V 1P8M no mimcap LVT	Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm CMOS – CMOS28LP Design Methodology: ST 28 nm FD-SOI CMOS Technology – Analog Design Flow and Reference Design Design Methodology: STMicroelectronics 28nm FD-SOI CMOS Technology Digital/Mixed-Mode Design Flow	$14,030/mm² (Minimum charge is for a 1.25 mm² design)	Microelectronics, Microelectronics Featured, STM	ST 28 nm FD SOI CMOS
Getter-free high-vacuum sealing allows resonator Q factors > 20,000 Efficient wafer-level packaging minimizes overall die size 1.5-μm feature size in a 30-μm thick membrane Comb height control allows out-of-plane sensing TSV allows compact design ready for co-packaging Deliver 40 copies for each design Sealed-cavity MEMS 30-μm structure layer High-vacuum	Teledyne DALSA MIDIS Design Kits	$9,750 (per 4 mm x 4 mm design)	industry, MEMS, Teledyne	Teledyne DALSA MIDIS Platform
Two thick SOI structure layers with up to three functional levels of silicon thickness option. This enables structures such as vertical comb-drive actuators. Base and top device layers are electrically connected through the bond interface, allowing 3D routing of electrical signals. Patterned low-stress gold metallization on the top surface is suited for highly reflective mirrors and contact pads for gold wire bonding. Design size 4 mm x 4 mm SOI MEMS Two structure layers Three trench depths	Design Kit: Micralyne MicraGEM-Si™, for Tanner L-Edit Design Handbook: Micralyne MicraGEM-Si™ (ICI-319)	Dedicated runs only. Contact [email protected].	MEMS, Teledyne	Teledyne Micralyne Micralyne MicraGEM-Si™ MEMS Process
1.2 V/3.3 V 1P8M mimcap		$2,583/mm² (Minimum charge is for a 25 mm² design)	Microelectronics, TSMC	TSMC 0.13 µm CMOS RF Mixed-Signal Process
1.8 V/3.3 V 1P6M mimcap LVT/native/HVT	For the X-dim.: the smallest size should be no less than 0.6mm The die aspect ratio (AR) should not exceed that of 3 to 1For TSMC 180nm MS RF G Specification Required die Y dimension (mm) (including seal ring): 2, 3, or 5 if metal option 1p6m_4X1U40KA (Strongly recommend 1p6M_4X1U40KA) is used; 3 or 5 if metal option 1p6m_4X1N8KA is used MiM cap. density, if used (fF/um2): 2 I/O (V): 3.3 Backgrind thickness (mils): 12	$1,794/mm² (Minimum charge is for a 5 mm² design)	Microelectronics, TSMC	TSMC 0.18 µm CMOS Process Technology
3.3 V/5 V 2P4M		$540/mm² (Minimum charge is for a 25 mm² design)	Microelectronics, TSMC	TSMC 0.35 µm CMOS Process Technology
0.9 V (core)/1.8 V (I/O) 1P9M (1P9M_6x1z1u) High K – Metal gate	Standard cell	$19,806/mm²	Microelectronics, Microelectronics Featured, TSMC	TSMC 28 nm CMOS Process Technology (HPC+RF)
1.0 V/2.5 V 1P9M mim/momcap LVT/native/HVT Constraints For TSMC 65nm MS RF GP Specification Requirements: Required die Y dimension (mm) (including seal ring): 1, 2, 3, etc. (must be in integer format) MiM cap. density, if used (fF/um2): 2 Metal: 1p9m_6X1Z1U AP layer thickness: 14.5KA I/O (V): 2.5	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 Design Kit: TSMC 65 nm CMOS GP – CRN65GP	$8,324/mm²	Microelectronics, TSMC	TSMC 65 nm GP CMOS Process Technology
1.2 V/2.5 V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Kit: TSMC 65 nm CMOS GP – CRN65LP Design Library: TSMC 65 nm LP Standard Cell Libraries – tcbn65lp Design Library: TSMC 65 nm LP IO Digital Libraries – tpdn65lpnv2 Design Library: TSMC 65nm LP IO Analog Libraries – tpan65lpnv2	$8,324/mm²	Microelectronics, TSMC	TSMC 65 nm LP CMOS Process Technology
Nb resonators with Q-factor of approximately one million Aluminum junctions		$30,000 (per 5 x 5 mm² design)	industry, Quantum Featured, VTT	VTT Aluminum Junction Process
One tri-layer for junctions and an additional metallic layer	Design Kit: VTT Niobium SWAPS Junction Process	Contact [email protected].	industry, Quantum Featured, VTT	VTT Niobium SWAPS Junction Process
Coming soon …		Coming soon …		X-FAB: XT018 Automotive 180 nm BCD-on-SOI Technology Platform