FAB

Available Technologies

Through supplier partnerships, we offer multi-project wafer services and related fabrication services in a variety of technologies. View our fabrication schedule online.

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Microelectronics

Photonics/Optoelectronics

MEMS

Experimental/Emerging Technologies

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Process Name	Features	Design Kit	Canadian Academic	Canadian Academic Peer Reviewed
STM 28 nm CMOS FDSOI Product Page	1.0/1.8V 1P8M no mimcap LVT	Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm CMOS – CMOS28LP Design Methodology: ST 28 nm FD-SOI CMOS Technology – Analog Design Flow and Reference Design Design Methodology: STMicroelectronics 28nm FD-SOI CMOS Technology Digital/Mixed-Mode Design Flow	$12,500/mm² (Minimum charge is for a 1.25 mm² design)	$5,000/mm²(Minimum charge is for a 1.25 mm² design)
TSMC 65 nm CMOS GP Product Page	1.0/2.5V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 Design Kit: TSMC 65 nm CMOS GP – CRN65GP	$5,200/mm²(Minimum charge is for a 1.1 x 1.1 mm² design)	$2,350/mm²(Minimum charge is for a 1.1 x 1.1 mm² design.)
TSMC 65 nm CMOS LP Product Page	1.2/2.5V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 Design Kit: TSMC 65 nm CMOS GP – CRN65GP	$5,200/mm²(Minimum charge is for a 1.1 x 1.1 mm² design)	$2,350/mm²(Minimum charge is for a 1.1 x 1.1 mm² design)
TSMC 0.13 μm CMOS Product Page	1.2/3.3V 1P8M mimcap	Design Kit: TSMC 0.13 µm CMOS	$2,050/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)	$1,025/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)
TSMC 0.18 μm CMOS Product Page	1.8/3.3V 1P6M mimcap LVT/native/HVT	Design Kit: TSMC 0.18µm CMOS Process Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Library: ARM Digital Standard Cell and IO Libraries for TSMC 0.18 µm CMOS Design Library: TSMC 0.18 µm CMOS Standard Cells Library – tsmc-cl018g_sc-x_2004q3v1 Design Flow: Digital IC Design (from RMC)	$1,100/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)	$425/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)
TSMC 0.35 μm CMOS Product Page	3.3/5V 2P4M	Design Kit: TSMC 0.35-micron CMOS-CM0SP35 Design Kit: TSMC 0.35 µm CMOS Process Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$475/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)	$250/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)
AMS 0.35 μm CMOS – Basic Product Page	3.3/5V 2P4M	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,200/mm²	$600/mm²
AMS 0.35 μm CMOS – Opto Product Page	3.3/5V 2P4M anti-reflective coating	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,200/mm²	$600/mm²
AMS 0.35 μm CMOS – High Voltage Product Page	3.3/5/50V 2P4MH35B4D3kit includes: standard cell IO bondpad	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,320/mm²	$600/mm²
Open-Gate Silicon JFET Product Page	JFET with no top gate, enabling user-deposition of sensor material 4-mask process on epitaxial Si with 5 µm feature size Front- and back-side Boron ion implantation One metal routing layer Gold pad metallization (compatible with wirebonding) SiN passivation Aluminum bottom gate	Design Kit: Open-Gate Silicon JFET (OG Si-JFET) in L-Edit and Synopsys Sentaurus	Contact fab@cmc.ca.
Silicon Photonics General-Purpose Product Page	SOI, 220 nm top Si, 2000 nm BOX 193 nm lithography for waveguides 6 implants for optical modulators Ge deposition & implanting for photodetectors Two metal levels for routing plus metal heater	Design Kit: Mentor Graphics Pyxis for the Advanced Micro Foundry (AMF) Silicon Photonics Fabrication Process Design Kit: Luceda-Tanner-AMF Silicon Photonics Design Platform	$14,000 (Per 3 x 8 mm² design)	$4,300 (Per 3 x 8 mm² design)
Global Foundries 130 nm BiCMOS SiGe 8HP Product Page	1.2/2.5V CMOS supply 1P8M process High-performance FETs ft/fmax 200/265GHz Twin well CMOS technology MIM/Dual MIM Capacitors Series/Parallel spirals Inductors µm/mm wave passive components Thin/Thick dual gate oxide	130HPSIGE-8HP V1.8_4.0	Contact fab@cmc.ca.
GF 90nm CMOS-photonics 9WG Product Page	SOI substrate Far-BEOL V-groove for fibre attach 1P7M LVT		Contact fab@cmc.ca.
III-V Epitaxy on GaAs Substrates, InP and Ge Substrates Product Page		Design Kit: CPFC Optoelectronic/Photonic III-V Process Epi-Structure Form	The cost is highly structural dependent. Please contact zhang@cmc.ca.
MEMSCAP PiezoMUMPs Product Page	SOI MEMS 25um structure layer piezoelectric metal	Design Kit: PiezoMUMPs for Tanner L-Edit and MEMS Pro Design Kit: PiezoMUMPs for Coventorware Design Kit: MEMSCAP PiezoMUMPs Design Handbook	$1,420 (per 5 x 5 mm² design)	$550 (per 5 x 5 mm² design)
MEMSCAP PolyMUMPs Multi-User MEMS Process Technology Product Page	Surface MEMS Three structure layers	Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0 Design Kit: PolyMUMPs Design Handbook for MEMSPro Design Kit: PolyMUMPs MEMS Process for CoventorWare	$1,420 (per 5 x 5 mm² design)	$550 (per 5 x 5 mm² design)
MEMSCAP Post-Processing for PolyMUMPs Product Page		Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0 Design Kit: PolyMUMPs Design Handbook for MEMSPro	$860/design	$325/per design
Teledyne DALSA MIDIS Platform Product Page		Teledyne DALSA MIDIS Design Kits	$9,800 (per 4 x 4 mm² design)	$3,400 (per 4 x 4 mm² design)
MicraGEM-Si™ MEMS Process Product Page		Design Kit: Micralyne MicraGEM-Si™, for Tanner L-Edit Design Handbook: Micralyne MicraGEM-Si™ (ICI-319)	Contact fab@cmc.ca.

Microelectronics

Process Name	Features	Design Kit	Canadian Academic	Canadian Academic Peer Reviewed
STM 28 nm CMOS FDSOI Product Page	1.0/1.8V 1P8M no mimcap LVT	Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm FD SOI CMOS – CMOS28FDSOI Design Kit: STM 28 nm CMOS – CMOS28LP Design Methodology: ST 28 nm FD-SOI CMOS Technology – Analog Design Flow and Reference Design Design Methodology: STMicroelectronics 28nm FD-SOI CMOS Technology Digital/Mixed-Mode Design Flow	$12,500/mm² (Minimum charge is for a 1.25 mm² design)	$5,000/mm²(Minimum charge is for a 1.25 mm² design)
TSMC 65 nm CMOS GP Product Page	1.0/2.5V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 Design Kit: TSMC 65 nm CMOS GP – CRN65GP	$5,200/mm²(Minimum charge is for a 1.1 x 1.1 mm² design)	$2,350/mm²(Minimum charge is for a 1.1 x 1.1 mm² design.)
TSMC 65 nm CMOS LP Product Page	1.2/2.5V 1P9M mim/momcap LVT/native/HVT	Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v Design Library: TSMC 65 nm GP Standard Cell Libraries – tcbn65gplus Design Library: TSMC 65 nm GP IO Digital Libraries – tpfn65gpgv2od3 Design Kit: TSMC 65 nm CMOS GP – CRN65GP	$5,200/mm²(Minimum charge is for a 1.1 x 1.1 mm² design)	$2,350/mm²(Minimum charge is for a 1.1 x 1.1 mm² design)
TSMC 0.13 μm CMOS Product Page	1.2/3.3V 1P8M mimcap	Design Kit: TSMC 0.13 µm CMOS	$2,050/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)	$1,025/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)
TSMC 0.18 μm CMOS Product Page	1.8/3.3V 1P6M mimcap LVT/native/HVT	Design Kit: TSMC 0.18µm CMOS Process Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Library: ARM Digital Standard Cell and IO Libraries for TSMC 0.18 µm CMOS Design Library: TSMC 0.18 µm CMOS Standard Cells Library – tsmc-cl018g_sc-x_2004q3v1 Design Flow: Digital IC Design (from RMC)	$1,100/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)	$425/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)
TSMC 0.35 μm CMOS Product Page	3.3/5V 2P4M	Design Kit: TSMC 0.35-micron CMOS-CM0SP35 Design Kit: TSMC 0.35 µm CMOS Process Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$475/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)	$250/mm² (Minimum charge is for a 1.1 x 1.1 mm² design)
AMS 0.35 μm CMOS – Basic Product Page	3.3/5V 2P4M	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,200/mm²	$600/mm²
AMS 0.35 μm CMOS – Opto Product Page	3.3/5V 2P4M anti-reflective coating	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed-Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,200/mm²	$600/mm²
AMS 0.35 μm CMOS – High Voltage Product Page	3.3/5/50V 2P4MH35B4D3kit includes: standard cell IO bondpad	Design Kit: AMS 0.35-micron CMOS Process Design Kit Design Methodology: Digital IC Design Flow Design Flow: Analog IC Design Methodology Kit: Cadence Analog/Mixed Signal (AMS) Design Flows Design Flow: Digital IC Design (from RMC)	$1,320/mm²	$600/mm²
Global Foundries 130 nm BiCMOS SiGe 8HP Product Page	1.2/2.5V CMOS supply 1P8M process High-performance FETs ft/fmax 200/265GHz Twin well CMOS technology MIM/Dual MIM Capacitors Series/Parallel spirals Inductors µm/mm wave passive components Thin/Thick dual gate oxide	130HPSIGE-8HP V1.8_4.0	Contact fab@cmc.ca.

Photonics/Optoelectronics

Process Name	Features	Design Kit	Canadian Academic	Canadian Academic Peer Reviewed
Silicon Photonics General-Purpose Product Page	SOI, 220 nm top Si, 2000 nm BOX 193 nm lithography for waveguides 6 implants for optical modulators Ge deposition & implanting for photodetectors Two metal levels for routing plus metal heater	Design Kit: Mentor Graphics Pyxis for the Advanced Micro Foundry (AMF) Silicon Photonics Fabrication Process Design Kit: Luceda-Tanner-AMF Silicon Photonics Design Platform	$14,000 (Per 3 x 8 mm² design)	$4,300 (Per 3 x 8 mm² design)
GF 90nm CMOS-photonics 9WG Product Page	SOI substrate Far-BEOL V-groove for fibre attach 1P7M LVT		Contact fab@cmc.ca.
III-V Epitaxy on GaAs Substrates, InP and Ge Substrates Product Page		Design Kit: CPFC Optoelectronic/Photonic III-V Process Epi-Structure Form	The cost is highly structural dependent. Please contact zhang@cmc.ca.

MEMS

Process Name	Features	Design Kit	Canadian Academic	Canadian Academic Peer Reviewed
MEMSCAP PiezoMUMPs Product Page	SOI MEMS 25um structure layer piezoelectric metal	Design Kit: PiezoMUMPs for Tanner L-Edit and MEMS Pro Design Kit: PiezoMUMPs for Coventorware Design Kit: MEMSCAP PiezoMUMPs Design Handbook	$1,420 (per 5 x 5 mm² design)	$550 (per 5 x 5 mm² design)
MEMSCAP PolyMUMPs Multi-User MEMS Process Technology Product Page	Surface MEMS Three structure layers	Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0 Design Kit: PolyMUMPs Design Handbook for MEMSPro Design Kit: PolyMUMPs MEMS Process for CoventorWare	$1,420 (per 5 x 5 mm² design)	$550 (per 5 x 5 mm² design)
MEMSCAP Post-Processing for PolyMUMPs Product Page		Design Kit: PolyMUMPs MEMS Process for MEMSPro V7.0 Design Kit: PolyMUMPs Design Handbook for MEMSPro	$860/design	$325/per design
Teledyne DALSA MIDIS Platform Product Page		Teledyne DALSA MIDIS Design Kits	$9,800 (per 4 x 4 mm² design)	$3,400 (per 4 x 4 mm² design)
MicraGEM-Si™ MEMS Process Product Page		Design Kit: Micralyne MicraGEM-Si™, for Tanner L-Edit Design Handbook: Micralyne MicraGEM-Si™ (ICI-319)	Contact fab@cmc.ca.

Experimental/Emerging Technologies

Process Name	Features	Design Kit	Canadian Academic	Canadian Academic Peer Reviewed	List
Open-Gate Silicon JFET Product Page	JFET with no top gate, enabling user-deposition of sensor material 4-mask process on epitaxial Si with 5 µm feature size Front- and back-side Boron ion implantation One metal routing layer Gold pad metallization (compatible with wirebonding) SiN passivation Aluminum bottom gate	Design Kit: Open-Gate Silicon JFET (OG Si-JFET) in L-Edit and Synopsys Sentaurus	Contact fab@cmc.ca.

FAB

Available Technologies

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