- Silicon nitride with device layer thickness 400 nm and buffer oxide Layer thickness 4.5 µm
- 100 keV electron-beam lithography system enabling features down to 120 nm
- Fully etched devices (etched down to the buffer oxide) are created using an e-beam mask material and anisotropic ICP-RIE etching process.
- Tri-layer TiW/Al metallization and TiW alloy heater are available
- Metal oxide window, deep trench for edge coupling and SEM imaging options are available.
- Supports design and fabrication of a range of components and systems consisting of:
- waveguides (strip)
- gratings for fibre coupling
- deep trench and nano-tapers for edge coupling
- multiplexers (diffraction or arrayed waveguide) and filters (resonators, Bragg gratings)
Applied Nanotools (ANT) Silicon Nitride (SiN) Fabrication Process
- SiN, 400 nm on 4.5 µm oxide box layer
- 100 keV electron-beam lithography for waveguides
- One metal level for routing plus metal heater
Design Kits and Libraries