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The Atlas 200 DK (model: 3000) is a high-performance AI application developer board that integrates the Ascend 310 AI processor to facilitate quick development and verification. It has been widely used in scenarios such as developer solution verification, higher education, and scientific research.

The Atlas 800 training server (model: 9000) is powered by the Kunpeng 920 and Ascend 910 processors. It features the industry’s highest computing density, ultra-high energy efficiency, and high network bandwidth. The server is widely used in deep learning model development and training scenarios and is an ideal option for computing-intensive industries, such as smart city, intelligent healthcare, astronomical exploration, and oil exploration.

BARVINN is a Barrel RISC-V Neural Network Accelerator. The main purpose of BARVINN is to fill the need for arbitrary precision neural network acceleration. The overall architecture of BARVINN consists of the following blocks:

• Array of Matrix Vector Units (MVU Array)
• RISC-V Controller Core
• Host Machine

The FPGA/GPU cluster is a cloud-based, remotely accessible compute infrastructure specifically designed to accelerate compute-intensive applications, such as machine learning training and inference, video processing, financial computing, database analytics networking and bioinformatics.

The Heterogeneous Computing Middleware Platform (HCMP) provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software. Complex tasks such as multi-device memory management, device I/O, kernel scheduling, and dependency management are handled by the platform so that users can focus on writing their applications instead of adhering to complicated specifications.

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The Heterogeneous Parallel Platform (HPP) is a highly customizable, flexible and extensible single node computing system integrating a variety of different types of computational units. The HPP brings together the latest technologies in multi-core CPUs, many-core GPUs, application-specific many-cores CPUs and FPGAs in a single prevalidated platform. The HPP development environment includes a complete ecosystem of tools, OS, hardware/Software IPs and reference designs.

The Microsystems Integration Platform (MIP) is a benchtop instrument intended for multi-technology validation of the functionality of a micro-device in a system context. Designed to enable proof-of-concept experiments at a laboratory-based system level, the MIP effectively bridges the gap between algorithmic/architectural exploration, stimulus, and measurement of sensors and actuators.

The MIP generic MEMS variant bridges the gap between algorithmic/architectural exploration and stimulus, and measurement of MEMS sensors and actuators. It presents a modular, desktop environment for MEMS and electronics device integration and validation in a system context.

The MIP generic MEMS variant has a PXIe-based control system, which includes a system-level design environment, data acquisition, FPGA-based imaging system, FPGA based signal/control processing and signal conditioning, as well as MEMS sensor and actuator interfaces for MEMS micro-device characterization and measurement.

The MIP Microfluidics variant bridges the gap between algorithmic/analysis and stimulus, and measurement of microfluidics bio-sensors and detectors. It presents a modular, desktop environment for microfluidics and electronics device integration and validation in a system context.

The MIP Microfluidics variant has a PXIe-based control system, which includes a system-level design environment, data acquisition, FPGA-based imaging system, FPGA based signal/control processing and signal conditioning, as well as Microfluidics fixtures or interface boards for Microfluidics device characterization and measurement.

The MIP Micromirror variant bridges the gap between algorithmic/analysis and stimulus, and measurement of MEMS micromirror sensors. It presents a modular, desktop environment for MEMS micromirror and electronics device integration and validation in a system context.

The MIP Micromirror variant has a PXIe-based control system, which includes a system-level design environment, data acquisition, FPGA based signal/control processing and signal conditioning, as well as Micromirror fixtures or interface boards for Micromirror device characterization and measurement.

The MIP RF-MEMS variant bridges the gap between algorithmic/analysis and stimulus, and measurement of MEMS RF-MEMS devices. It presents a modular, desktop environment for RF-MEMS and electronics device integration and validation in a system context.

The MIP RF-MEMS variant has a PXIe-based control system, which includes a system-level design environment, RF signal/vector generator, RF signal/vector analyzer, as well as RF switches and fixtures for RF-MEMS device characterization and measurement.

The MIP variant for Si-photonic hardware in the loop bridges the gap between algorithmic/architectural exploration and stimulus, and measurement of photonic hardware in the loop of a prototype microsystem. It presents a modular, desktop environment for Si-photonic chip prototyping in a system context.

The Multiprocessor Array (MPA) Platform consists of a General-Purpose Graphics Processing Unit (GP-GPU) and a compatible host workstation/server, or multi-core processor technology featured for parallel computing such as Intel Knights Landing. The platform enables researchers to accelerate processing of algorithms and simulations, and explore topics such as multi-core software authoring, modeling, computer architecture, and novel approaches to power-efficient high-performance computing.

The Real-time Embedded Systems Lab (RESL) at the University of Waterloo focuses on real-time embedded software and systems that are at the intersection of software technology, embedded networking, and applied formal methods. Real-time embedded systems are characterized by their interaction with the environment through sensors and actuators, their resource-constrained platforms, and non-functional properties. Part of the Embedded Systems Canada CFI project, the RESL is staffed by a full-time software engineer and is open to both academic and industrial use.

RESL Contact

Dr. Sebastian Fischmeister
University of Waterloo E5-4112
Waterloo, ON N2L 3G1
Phone: 1.519.888.4567 ext:33694
Email: sfischme@uwaterloo.ca

RISC-V is a free, open instruction set architecture, (ISA) that enables processor innovation through open standard collaboration. The RISC-V ISA provides the research community with an opportunity for innovation in new system products, particularly for machine learning and edge computing.

The SOSCIP Agile Computing Platform consists of a set of supported online FPGA Systems, including Nallatech PCIe-385N and Alpha Data PCIe-8K5 boards housed in x86 and Power8 Servers. These FPGA boards can be programmed using OpenCL and make use of IBM’s CAPI interface, which allows the FPGA and Power8 processor to operate in a peer-to-peer coherent relationship. Suitable applications include compute-intensive tasks requiring efficient server-side processing in areas such as health, machine learning, signal processing, Monte Carlo simulations, and big data analytics.

The SwiftMote Sensor Platform is a Bluetooth wireless sensor mote. SwiftMote is an open platform designed to be a proving ground for your novel sensors and packaging research to showcase to investors. Jump-start your research by using SwiftMote out of the box or customize to suit your R&D needs. SwiftMote includes everything needed to sense the environment, store the data, and forward the Information to a phone using Bluetooth.

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The ZCU102 is a high-performance, high-speed hardware/software design platform providing the integration of hardware, software, IP, and reference designs which enables quicker time-to-innovation for researchers. Based around the Xilinx Zynq Ultrascale+ MPSoC, it is equipped with industry-standard peripherals, connects, and interfaces that offer a rich set of features suitable for a wide range of applications.

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The ML605 is a high-performance, high-speed FPGA design platform providing the integration of hardware, software, IP, and reference designs which enables quicker time-to-innovation for researchers. Based around the Xilinx Virtex-6 FPGA ML605 Evaluation Kit, it is equipped with industry-standard peripherals, connects, and interfaces that offer a rich set of features suitable for a wide range of applications.

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