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The Atlas 200 DK (model: 3000) is a high-performance AI application developer board that integrates the Ascend 310 AI processor to facilitate quick development and verification. It has been widely used in scenarios such as developer solution verification, higher education, and scientific research.

The Atlas 800 training server (model: 9000) is powered by the Kunpeng 920 and Ascend 910 processors. It features the industry’s highest computing density, ultra-high energy efficiency, and high network bandwidth. The server is widely used in deep learning model development and training scenarios and is an ideal option for computing-intensive industries, such as smart city, intelligent healthcare, astronomical exploration, and oil exploration.

BARVINN is a Barrel RISC-V Neural Network Accelerator. The main purpose of BARVINN is to fill the need for arbitrary precision neural network acceleration. The overall architecture of BARVINN consists of the following blocks:

• Array of Matrix Vector Units (MVU Array)
• RISC-V Controller Core
• Host Machine

An AutoML studio to create faster, smaller, more power efficient deep learning models for various hardware backends.

The FPGA/GPU cluster is a cloud-based, remotely accessible compute infrastructure specifically designed to accelerate compute-intensive applications, such as machine learning training and inference, video processing, financial computing, database analytics networking and bioinformatics.

The Heterogeneous Computing Middleware Platform (HCMP) provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software. Complex tasks such as multi-device memory management, device I/O, kernel scheduling, and dependency management are handled by the platform so that users can focus on writing their applications instead of adhering to complicated specifications.

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The Heterogeneous Parallel Platform (HPP) is a highly customizable, flexible and extensible single node computing system integrating a variety of different types of computational units. The HPP brings together the latest technologies in multi-core CPUs, many-core GPUs, application-specific many-cores CPUs and FPGAs in a single prevalidated platform. The HPP development environment includes a complete ecosystem of tools, OS, hardware/Software IPs and reference designs.

RISC-V is a free, open instruction set architecture, (ISA) that enables processor innovation through open standard collaboration. The RISC-V ISA provides the research community with an opportunity for innovation in new system products, particularly for machine learning and edge computing.

The SwiftMote Sensor Platform is a Bluetooth wireless sensor mote. SwiftMote is an open platform designed to be a proving ground for your novel sensors and packaging research to showcase to investors. Jump-start your research by using SwiftMote out of the box or customize to suit your R&D needs. SwiftMote includes everything needed to sense the environment, store the data, and forward the Information to a phone using Bluetooth.

The Xilinx VCK190 Versal AI Core Series Evaluation Kit allows designers to develop solutions using specialized AI and DSP engines to deliver over 100x greater compute performance compared to current server class CPUs. The kit offers connectivity and memory options and is supported by the latest Xilinx development tools and flows.

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The ZCU102 is a high-performance, high-speed hardware/software design platform providing the integration of hardware, software, IP, and reference designs which enables quicker time-to-innovation for researchers. Based around the Xilinx Zynq Ultrascale+ MPSoC, it is equipped with industry-standard peripherals, connects, and interfaces that offer a rich set of features suitable for a wide range of applications.

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Xilinx’s Radio Frequency System-on-Chip (RFSoC) devices have created a new class of integrated circuit architecture for the communications and instrumentation markets. RFSoCs combine high-accuracy ADCs and DACs operating at Giga samples per second with programmable heterogeneous compute engines.

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