RISC-V is a free, open instruction set architecture, (ISA) that enables processor innovation through open standard collaboration. The RISC-V ISA provides the research community with an opportunity for innovation in new system products, particularly for machine learning and edge computing.
CMC helps realize RISC-V designs by offering:
- Silicon-proven design platforms based on OpenHW Group CORE-V family of open-source cores
- CAD tools and flows for virtual system prototyping and ASIP design, physical implementation, PCB design, and software development
- Industry-standard tools from Cadence Design Systems, Synopsys, and Mentor Graphics
- CMC Cloud access, pre-configured to ensure quick and easy desktop use
- FPGA platforms for system emulation and validation, early software bring-up and debug
- Available on-site, through short-term rental or via CMC cloud access
- Design kits for fabrication in commercial technologies from 350 nm down to 22 nm
- Including digital cells, memory, and I/O blocks
- Multi-project wafer services for fabrication
- Packaging and assembly services
- Access to test equipment
CORE-V MCU is a single-core RISC-V microcontroller architecture based on the CV32E40P 32-bit RISC-V core from OpenHW Group. This platform includes:
- Open source SystemVerilog code for processor and peripherals
- FPGA emulation targeting Digilent NexysA7 and Genesys2 FPGA platforms
- In development: SOC implementation in Global Foundries 22 nm FDX technology with embedded FPGA fabric from QuickLogic for custom accelerators; development boards expected Q2 2021
The main repository for this platform is: https://github.com/openhwgroup/core-v-mcu.
CMC has several active R&D projects supported through Mitacs to develop and prototype RISC-V platforms, including:
- DNA sequencing accelerator in GF 22-nm CMOS
- Machine learning accelerator on FPGA
Project outputs will be hosted in CMC’s Github as they become available: https://github.com/cmcmicrosystems.
Pulpissimo for ZCU102 – an open-source single-core RISC-V SoC platform that runs on Xilinx ZCU102 evaluation board.