CMC offers access to the TSMC 65 nm LP CMOS technology. Access is limited to account holders who are approved by TSMC. To access this technology, please contact [email protected].
CMC is offering access to this 65 nm LP CMOS through TSMC’s shuttle service. The process flavour supported by CMC is:
- Mixed-signal/RF 1P9M process configured for 1.2/2.5 V and ultra-thick (34 kA) top metal options which is suitable for:
- Low power circuits
- RF/mixed-signal designs
- High-speed digital circuits
- Potential applications include:
- RF, microwave systems
- Optical communication systems
Note: The expected number of chips to be delivered for this technology is 100.
Constraints
- Required die Y dimension (mm) including seal ring: 1, 2, 3, etc., must be in integer format.
Note: The Y dimension has 10% shrinkage. To meet the Y dimension requirement, the designed Y should be 1.111, 2.222, 3.333, and so forth. When measuring the area, the shrunk size will be considered. - Required die X dimension including seal ring: minimum 0.6 mm
- minimum area: 1 mm2
- aspect ration <=3Â
- MiM cap. density, if used: 2 fF/um2
- Metal: 1p9m_6X1Z1U
- AP layer thickness: 14.5 KA
- I/O: 2.5 V
