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TSMC 65 nm LP CMOS Process Technology

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Description

CMC offers access to the TSMC 65nm LP CMOS technology. Access is limited to account holders who are approved by TSMC. To access this technology, please contact licensing@cmc.ca.

CMC is offering access to this 65nm LP CMOS through TSMC’s shuttle service. The process flavour supported by CMC is:

  • Mixed-signal/RF 1P9M process configured for 1.2/2.5V and ultra-thick (34kA) top metal options which is suitable for:
    • Low power circuits
    • RF/mixed-signal designs
    • High-speed digital circuits
  • Potential applications include:
    • RF, microwave systems
    • Optical communication systems

Note: The expected number of chips to be delivered for this technology is 100.

Features

  • 1.2 V/2.5 V
  • 1P9M
  • mim/momcap
  • LVT/native/HVT

Design Kits and Libraries

  • Design Library: TSMC 65 nm GP Bond Pad Library – tpbn65v
  • Design Kit: TSMC 65 nm CMOS GP – CRN65LP
  • Design Library: TSMC 65 nm LP Standard Cell Libraries – tcbn65lp
  • Design Library: TSMC 65 nm LP IO Digital Libraries – tpdn65lpnv2
  • Design Library: TSMC 65nm LP IO Analog Libraries – tpan65lpnv2

Pricing

List Price
Price for Subscribers

Note: List pricing is in US funds and does not include engineering support. Contact fab@cmc.ca for a quote.

Note: Discounted pricing is available to academics in Canada with a CMC Subscription. You must sign in to see it.

Licensing

Minimum Access Requirement

For Canadian Academics

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