CMC Microsystems, the CMC Microsystems logo, CMC Basecamp, CMC SponsorChip, CADpass, Canada’s National Design Network and Réseau National de Conception du Canada are trademarks or registered trademarks of Canadian Microelectronics Corporation / Société canadienne de micro-électronique operating as CMC Microsystems.
ASIP Designer Workshop
October 17, 2019 at Montréal, Quebéc Discover how Synopsys ASIP Designer can enhance your research using custom processors and programmable hardware accelerators. Join CMC Microsystems and Synopsys, Inc. at
October 17, 2019 at Montréal, Quebéc
Discover how Synopsys ASIP Designer can enhance your research using custom processors and programmable hardware accelerators. Join CMC Microsystems and Synopsys, Inc. at Polytechnique Montréal for a 1/2-day workshop demonstrating the capabilities and benefits of the ASIP Designer environment for applications such as AI and 5G. The workshop will showcase industrial and academic case studies and tool demonstrations.
|1:30 pm||Getting started: Application-specific processors (ASIPs) in system-on-chip design: market and technology trends (Synopsys)
Abstract: ASIPs have established themselves as an implementation option next to standard processor IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability. This talk will provide an introduction to the ASIP approach, will introduce Synopsys’ ASIP Designer tool-suite, targeted markets, and how Synopsys collaborates with university partners in this domain.
|2:15 pm||Designing an ASIP for SHA256 secure hashing, starting from a RISC-V ISA specification (including tool demonstration, Synopsys)
Abstract: Many embedded applications rely on hashing algorithms to transmit and to store data in a safe way. Examples are wired and wireless communication and solid-state storage. In these contexts, the hashing of data has to be executed at the rate used for the transmission of the data over a channel or stored to solid-state memory. At these high rates, ASIPs are an efficient way to implement hashing algorithms. In this session, we will look at how a standard algorithm, SHA256, can be accelerated by combining custom data paths, register and memory structures with instruction and data-level parallelism.
|3:30 pm||University case studies (Polytechnique Montréal, CMC Microsystems)|
|4:00 pm||Designing Application-Specific Processors for Deep Learning Acceleration (including tool demonstration, Synopsys)
Abstract: Deep learning is making its way into various application domains. The embedded vision market has embraced deep learning algorithms based on convolutional neural networks (CNN). Algorithms capturing dynamic temporal behavior in the form of recurrent neural networks (RNN) are being applied for sound processing and language translation systems. In such a dynamic environment, traditional SoC architectures with a microprocessor and hardwired accelerators no longer suffice. We will illustrate by example how ASIPs reconcile the needs for performance and flexibility. In this session, we will present ASIP architectures for two deep learning functions: (i) the acceleration of activation functions in LSTM networks, and (ii) simultaneous localization and mapping (SLAM).
|5:00 pm||Minimum Mean Square Error (MMSE) Equalization in 5G New Radio (Synopsys)
Abstract: ASIPs see strong adoption in the field of 5G wireless communication. ASIPs enable product development before the 5G standard is finally frozen. At the same time, ASIPs provide the acceleration needed to achieve the high throughput and short-latency requirements of 5G. As an example, we will show the design of an ASIP for MMSE in 5G New Radio. We follow an “algorithm first” design process. Such process starts from a number of algorithms for which the architecture has to be optimized, and the definition of the throughput requirements. The presentation will provide an overview of the main functional kernels of the MMSE algorithm, and the performance requirement in the context of the 5G standard. We will illustrate the architectural decisions that have to be taken, and how this process is being supported by ASIP Designer.
|5:30 pm||Workshop close|
Pricing and Registration
This workshop is part of the program of DASIP 2019 (Conference on Design and Architectures for Signal and Image Processing), October 16 to 18. To attend, there are two options:
|Option 1: Attend the full DASIP conference.|
|Option 2: Attend the ASIP Designer Workshop only:
(Thursday) 7:52 pm - 7:52 pm