ASIP Designer Workshop

October 17, 2019, at Montréal, Québec

Discover how Synopsys ASIP Designer can enhance your research using custom processors and programmable hardware accelerators. Join CMC Microsystems and Synopsys, Inc. at Polytechnique Montréal for a 1/2-day workshop demonstrating the capabilities and benefits of the ASIP Designer environment for applications such as AI and 5G. The workshop will showcase industrial and academic case studies and tool demonstrations.


Time Description
12:00 pm Lunch
1:30 pm Getting started: Application-specific processors (ASIPs) in system-on-chip design: market and technology trends (Synopsys)
2:15 pm Designing an ASIP for SHA256 secure hashing, starting from a RISC-V ISA specification (including tool demonstration, Synopsys)
3:15 pm Break
3:30 pm University case studies (Polytechnique Montréal, CMC Microsystems)
4:00 pm Designing Application-Specific Processors for Deep Learning Acceleration (including tool demonstration, Synopsys)
5:00 pm Minimum Mean Square Error (MMSE) Equalization in 5G New Radio (Synopsys)
5:30 pm Workshop close

Pricing and Registration

This workshop is part of the program of DASIP 2019 (Conference on Design and Architectures for Signal and Image Processing), October 16 to 18. To attend, there are two options:

Options Registration
Option 1: Attend the full DASIP conference.
Option 2: Attend the ASIP Designer Workshop only:

Planning an event, course or departmental meeting? CMC is interested in in your events.

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