Semiconductor Upskilling Training Program

What happens if I miss a live lecture or lab?
All live lecture and lab sessions are recorded and made available within 24 hours. Participants have on-demand access to recordings and the cloud lab environment for 3 months following the cohort end date.

How is cloud compute and IP secured?
All lab exercises are hosted on CMC’s dedicated, secure cloud infrastructure. Trainees work within isolated user sandboxes using generic industrial design kits (e.g., 45nm GPDK). No proprietary company IP is uploaded or required.

How much does a seat cost, and how does my company qualify for the $1,500 CAD FABrIC rate?
Standard tuition is $3,000 CAD per seat. Incorporated Canadian semiconductor, hardware, or microelectronics companies can register with FABrIC at no cost to unlock the subsidized $1,500 CAD rate for all full-time employees. If you are unsure of your company’s FABrIC status, contact Industry Engagement before checkout.

What are the prerequisites?
Prerequisites vary by discipline. Digital and verification tracks typically require basic digital logic and Verilog fluency. Advanced tracks (Memory, SerDes, CMOS Photonics) assume familiarity with fundamental transistor or circuit theory. Detailed prerequisites are listed on each individual course page.

What are the requirements to receive the CMC Certificate of Completion?
To receive the formal micro-credential, participants must attend at least 75% of live lectures and labs (or verified asynchronous review) and successfully submit all required laboratory design milestones for verification.

Who teaches the courses, and how is the curriculum validated?
Courses are led by active industry practitioners, principal consultants, and university researchers with production silicon experience (such as Polytechnique Montréal faculty for Digital IC Physical Design). Every syllabus is reviewed and pressure-tested through CMC’s Industry Training Advisory Group (ITAG), which includes engineering leaders from Qualcomm, AMD, Intel, TSMC, Cadence, Siemens EDA, GlobalFoundries, Alphawave Semi, and Fidus Systems.

Which EDA tools and process design kits (PDKs) are used in the labs?
ASIC tracks run on 100% cloud-hosted Cadence design environments (Virtuoso, Spectre, Innovus, and Xcelium) paired with a 45nm GPDK. Using the 45nm GPDK eliminates the 6-to-9 month foundry NDA delays that normally stall corporate onboarding, while teaching the exact Cadence simulation, extraction, and signoff workflows engineers apply to proprietary sub-7nm nodes. (Hosted cloud labs use Cadence tools exclusively; Siemens EDA participates as an ITAG curriculum advisor.)

What is the weekly time commitment for working engineers?
Each 8-week cohort is structured around full-time engineering schedules, requiring a maximum of 4 live hours per week (2 hours of live lecture and 2 hours of guided lab). All cloud-hosted Cadence environments remain accessible 24/7 for asynchronous lab completion, and cohorts are capped at 40 seats per track to maintain direct instructor and TA support.

What do participants build during the program?
Trainees complete and simulate production-style design blocks reviewed against industrial design rules rather than passive multiple-choice quizzes. Depending on the track, deliverables include netlist-to-GDSII physical implementations in Cadence Innovus, constrained-random SystemVerilog/UVM verification testbenches, or PAM-4 CTLE/DFE transceiver simulations.

Who is CMC Microsystems?
CMC Microsystems brings over 40 years of national leadership managing Canada’s National Design Network (CNDN), providing Canadian researchers and microelectronics companies with access to commercial EDA toolchains, test equipment, and silicon fabrication.