Building on the success of the Advanced CMOS workshop series in 2019-20, AMS training in March 2020, and the first delivery of this training in May/August 2021 CMC provides this training in partnership with Cadence Design Systems and GlobalFoundries®.
This is an advanced course that trains students in the Analog-Mixed Signal Design Methodology using Cadence tools targeting the GF12LP FinFET PDK. Course participants will have an opportunity to fabricate a chip targeting the GF12LP PDK facilitated by CMC. Participants are provided with the opportunity to fabricate their designs following the course. The training material has been developed by Cadence.
- This course is not for beginners and requires familiarity with Cadence tools and prior chip fabrication experience.
- Supervisors/Professors are to ensure they can check all the boxes in the Pre-requisites section prior to approving their students’ registration.
- Because course participants will have access to other proprietary and confidential information during the course, each participant is required to sign an Access to Intellectual Property & Non-Disclosure Agreement. Participants will be provided with the agreement by Sarah Neville (Neville@cmc.ca) during the registration process.
- To ensure compliance with various US and Canadian governmental export control regulations and those required by the technology suppliers, you must be physically situated within Canada while taking this course.
|March 7, 9, 11, 15, and 17||12:30 p.m. to 5:30 pm||Online-Virtual session|
|12:30 p.m. to 2:00 p.m.||Lecture, Demo, and Lab start.|
|2:00 p.m. to 2:30 p.m.||Break|
|2:30 p.m. to 5:30 p.m.||Self-paced Lab work|
|March 8, 10, 14, 16, and 18||1:00 p.m. to 3:00 p.m.||Office Hours: Cadence Engineers will be available to answer your questions related to the Labs|
- 3D FinFET transistor technology on 12 nm CMOS technology
- Standard cells and IP libraries are from IP vendors (Users to arrange access. Not through CMC)
- GF12LP Features:
- Logic Voltages → Vnom: 0.8 V, Vmax: 0.945 V
- 4 VTs: SLVT / LVT / RVT / HVT
- IO offering: 1.2 V, 1.35 V, 1.5 V and 1.8 V EG Devices
- Well resistor, precision MOL resistor, MIM / MIM4 / APMOM / MOS / VNCAP capacitors, ESD, eFuse, VPNP, VNPN and Diodes, Inductors, Transmission line
- Interlevel Low-K and Ultralow-K dielectrics
- Packaging options: C4 solder, Round or Oblong Copper Pillar Bump, Micro pillar Bump
- Fabrication is carried out at a GF FAB in USA.
Reference Design, Design Flow, and Labs
The Reference Design is developed using the GF12 FinFET process and will include both analog and digital blocks.
- Schematic preparation
- Layout and placement preparation
- Layout routing
- Layout finishing
- Digital design flow for mixed-signal
The Reference Flow Documentation has been developed as a collection of lectures, each demonstrating a separate portion of the development. The documentation will be delivered in PDF format and soft copies will be provided to the students and marked confidential information. Hard copies will not be provided.
All supervisors must be able to check off on all the following boxes to ensure their students/research staff have completed the prerequisites before their registration request is processed for the course (Limit: 30 attendees):
Recommended review of concepts
- FinFET Semiconductor Structure and Function by ThresholdSystems
- FinFET Fundamentals by Prof. Carusone
- Webinar How Row-Based Methodology Improves Custom Layout
Registration for the course will be opened once you complete the pre-requisites. The price for registration is $500 for a CMC subscriber.
Course cancellations must be received in writing at least one (1) week before the beginning date of the course in question to receive a full refund of the registration fee. A cancellation made after the deadline will not receive a refund. CMC Microsystems makes no commitments on refunds for travel or accommodations.