CMC Microsystems is pleased to organize the fourth workshop on accelerating AI, highlighting the challenges and opportunities of AI acceleration from the cloud to the edge. This workshop aims to bring together experts from industry and academia to share their latest achievements and innovations in AI and machine learning, hardware/software co-design, and best-in-class microarchitectures from the cloud to deeply embedded systems.
- ML applications: Computer Vision, NLP, EDA, CAD, etc.
- Novel AI HW: GPUs, FPGAs and Custom Accelerators
- Software stack: libraries, compilers, and ML frameworks
- ML Benchmarking on Emerging Hardware
- AI Latest trends in chip design and commercialization.
This workshop will
- Promote innovation, adoption and early access to advanced technologies, including silicon and systems for accelerating AI workloads from the cloud to the edge.
- Share insights and experiences with others; explore collaboration opportunities and connect leaders from the industry to AI researchers and start-ups.
- Influence technology selection (roadmap) and development activities of emerging AI trends.
The workshop is open to professors, research associates and graduate students at Canadian universities, as well as industrial attendees who wish to provide input and advice.
|May 4, 2023||1:00 pm to 5:00 pm EDT||Online|
|Time||Presenter||Organization||Title (click URL where applicable for the presentation)|
|1:00 – 1:10||Yassine Hariri||CMC Microsystems||Welcome and Opening Remarks|
|1:10 – 1:30||Rick O’Connor||OpenHW Group||CORE-V Cores: Open-Source RISC-V Cores for Industry & Academia|
|1:30 – 1:50||Gaurav Singh||Untether AI||Energy-Efficient AI Inference Acceleration with Untether AI|
|1:50 – 2:10||Griffin Lacey||Nvidia||Accelerating Transformers with FP8|
|2:10 – 2:30||Davis Sawyer||Deeplite||Running 2bit Quantized CNNs on Arm CPUs|
|2:30 – 2:40||Break|
|2:40 – 3:00||Andreas Moshovos||University of Toronto||Capitalizing on a Decade of Machine Learning Accelerators: SW/HW Assists for Training and Inference|
|3:00 – 3:20||Warren Gross||McGill University||Standard Deviation-Based Quantization for Deep Neural Networks|
|3:20 – 3:40||Nizar El Zarif||Polytechnique Montréal||Polara: A RISCV Multicore Vector Processor|
|3:40 – 4:00||François Leduc-Primeau||Polytechnique Montréal||Designing Robust DNN Models That Exploit Energy-Reliability Tradeoffs|
|4:00 – 4:30||Open Discussion|
Pricing and Registration
Yassine Hariri, Hariri@cmc.ca, CMC Microsystems
Over 15 years of experience in advanced computing systems from the cloud to the very edge, with a focus on artificial intelligence, computer vision, video, image and sensor fusion workloads acceleration, FPGA based prototyping, software stack, and domain-specific hardware architectures. Currently leading projects related to the specification, development, implementation, deployment, and support of the next generation of advanced computing infrastructure mainly FPGAs, GPUs, and Custom Hardware for AI applications. Dr. Hariri earned his B.A.Sc. in Computer Engineering from Ecole Marocaine des Sciences de l’ingénieur, Casablanca, Morocco, in 1998, and the M.S. and Ph.D. degrees from Ecole de Technologie Supérieure (ETS), Montreal, QC, Canada, in 2002 and 2008, respectively, all in electrical engineering.
If you have any comments or questions regarding the contents of this workshop, please contact Dr. Yassine Hariri at Hariri@cmc.ca.
Course cancellations must be received in writing at least one (1) week before the beginning date of the course in question to receive a full refund of the registration fee. A cancellation made after the deadline will not receive a refund. CMC Microsystems makes no commitments on refunds for travel or accommodations.