LTCC A6M Shared Run at ÉTS

Description

The LTCC A6M Shared Run is a standardized MPW-style prototyping option for ceramic circuits and substrates built on Ferro A6M material. It combines a fixed stack-up with an available PDK, L-Edit layer definitions, and fast/slow DRC rule sets to support manufacturable submissions.

The LTCC@ETS platform offers an LTCC A6M Shared Run for multi-layer ceramic prototyping based on a fixed seven-layer stack. The shared run is intended for users who want access to a standardized LTCC process with design-rule support and repeatable fabrication conditions.

The shared run uses Ferro A6M tape and a predefined layer build of 182 µm / 182 µm / 89 µm / 35 µm / 89 µm / 182 µm / 182 µm, for a total fired thickness of approximately 941 µm ±1%. Top and bottom layers use solderable gold conductors, while the internal routing layers use silver conductors.

This offering supports high-frequency and compact ceramic designs while keeping the process constrained for MPW access. In this shared run, open and closed cavities are not offered, and resistors are available on layer 7 only. Projects that need more flexibility can be addressed through a dedicated LTCC fabrication flow. 

Applications

The LTCC A6M Shared Run is suited to a wide range of compact ceramic and high-frequency implementations, including:

  • Ceramic packaging and interposers
  • Low-loss RF, microwave, and mm-wave circuits
  • Compact passive structures and lumped-element networks
  • Thermal management through metallized vias
  • High-density interconnect substrates for wire-bond or flip-chip assembly
  • Research and prototyping designs that benefit from a standardized LTCC stack and rule deck

Support

  • Designers should review the LTCC A6M Shared Run PDK during the design phase and run DRC before submission.
  • The shared run requires a single GDS or DXF database at 1:1 scale. Export in GDSII stream format and make sure the topcell name matches the design name.
  • Layouts should merge all layer structures properly, and vias should be drawn as circular features only, without overlapping circles on the same layer.
  • For design-rule and access support, contact [email protected].

Related Services

Additional services relevant to the LTCC A6M Shared Run include:

  • DRC and engineering support for LTCC layout preparation
  • Wire bonding or bumping on the shared-run solderable gold surfaces
  • X-ray internal structure inspection
  • Electrical characterization using network and spectrum analyzers
  • Dedicated LTCC fabrication for projects that require cavities or greater process flexibility beyond the shared run

Features

  • Ceramic packaging and interposers
  • Low-loss RF, microwave, and mm-wave circuits
  • Compact passive structures and lumped-element networks
  • Thermal management through metallized vias
  • High-density interconnect substrates for wire-bond or flip-chip assembly
  • Research and prototyping designs that benefit from a standardized LTCC stack and rule deck

Design Kits and Libraries

Participation and Pricing

For shared-run participation, tile options, and pricing details, contact [email protected].

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