FAB

Open-Gate Silicon JFET

Description

Silicon Junction Field Effect Transistors are fabricated at 3IT.Nano and delivered with an open upper gate for the integration of solution-processed functional materials. The platform is useful for the study and optimization of novel hybrid material systems in silicon and the realization of high-performance CMOS-compatible detectors.

Features

  • 4-mask process on epitaxial Si with 5 µm feature size
  • Front- and back-side Boron ion implantation
  • Aluminum-silicon metallization
  • SiN passivation
  • Backside gate
  • JFET with unpassivated gate, enabling user-deposition of sensor material
  • One metal routing layer
  • Silicon substrate

Services

  • Cloud design environment (includes process design documents, layout template, reference design and simulation for IR light detector using quantum dots)
  • Test fixture with ports for optical input and gas ambient control
  • DRC and engineering support for OG Si-JFET design
  • Sub-dicing (optional)
  • Mounting and wirebonding in ceramic pin grid array package

Applications

  • Optical detection using quantum dots, perovskites, nanostructured semiconductors, organic molecules and polymers
  • Biomarker detection using immobilized probes

Pricing

Contactfab@cmc.ca.

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