Open-Gate Silicon JFET


Silicon Junction Field Effect Transistors are fabricated at 3IT.Nano and delivered with an open upper gate for the integration of solution-processed functional materials. The platform is useful for the study and optimization of novel hybrid material systems in silicon and the realization of high-performance CMOS-compatible detectors.

Silicon Junction Field Effect Transistor
Note: The expected number of chips to be delivered for this technology is 11 (10 x 10 mm).


  • JFET with no top gate, enabling user-deposition of sensor material
  • 4-mask process on epitaxial Si with 5 µm feature size
  • Front- and back-side Boron ion implantation
  • One metal routing layer
  • Gold pad metallization (compatible with wirebonding)
  • SiN passivation
  • Aluminum bottom gate


  • Optical detection using quantum dots, perovskites, nanostructured semiconductors, organic molecules and polymers
  • Biomarker detection using immobilized probes


  • Cloud design environment (includes process design documents, layout template, reference design and simulation for IR light detector using quantum dots)
  • DRC and engineering support for OG Si-JFET design
  • Sub-dicing for 5×5 mm dice (optional)
  • Mounting and wirebonding in ceramic pin grid array package (optional)


Subscribers (Academics in Canada)

(Per 10 x 10 mm2 design)

Subscribers (Academics in Canada, Peer Reviewed)

(Per 10 x 10 mm2 design)

Academics outside of Canada or Industry
Contact fab@cmc.ca for MPW access, or sales@cmc.ca for a dedicated run.


Terms and conditions License Grant.

Minimum Subscription Required: Research

To Apply

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