Aaron Wang

Mini-Circuits Wideband Amplifier 0.1 to 18 GHz

Features Multiple, independent channels per radio and multiple radios per Access Point that deliver exceptional throughput advantages over convention Access Points 162 Mbps per radio – basic (3-channel) configuration provides over 50x increased throughput performance versus single-channel access points Uses industry-leading, proprietary data converter technology Roving Monitor that acts as a sniffer looking for rogue […]

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Other Ways to Run HPC (High-Performance Compute) Simulations

Some subscribers are interested in running large-scale CAD (Computer Aided Design) simulations and have booked time on Digital Research Alliance of Canada (“The Alliance”) nodes in which they install or use existing CAD installations. They would then like to connect their software and nodes to a CMC licence server and run simulations.  https://docs.alliancecan.ca/wiki/Technical_documentation  To set

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Edgewater Wireless EAP3031 Spectrum Slicing Access Point

Features Multiple, independent channels per radio and multiple radios per Access Point that deliver exceptional throughput advantages over convention Access Points 162 Mbps per radio – basic (3-channel) configuration provides over 50x increased throughput performance versus single-channel access points Uses industry-leading, proprietary data converter technology Roving Monitor that acts as a sniffer looking for rogue

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Running Ansys Fluent in Batch Mode on a Linux-based Cluster Using LSF Job Schedule

The following are guidelines for running a Fluent simulation in our CAD Compute Cluster.  Background With Ansys, you can generally read an older project in a newer version of the software, but you will have difficulty viewing projects created in newer versions from within older releases. It is good practice to use the same release

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Guide to Ansys Electronics Desktop (EDT) Simulation in the CAD Compute Cluster

This page offers guidance for running Ansys Electronics Desktop using an LSF Job Scheduler (command line; without GUI) in our CAD Compute Cluster.  More information about the Load Sharing Facility (LSF) job scheduler is provided here. Our Cluster operates using the Linux operating system. We provide some basic information about Linux and Linux commands here and

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Research Workshop – Secure IoT Hardware

Description While the Internet of Things (IoT) promises billions of connected sensing devices collecting, processing, and communicating unprecedented amounts of data, each device represents a potential access point for security breaches that expose personal information or cause harm to human life or essential infrastructure. Through presentations and open discussion, this 1/2-day virtual workshop will bring

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Accelerating AI Workshop 2022 – Challenges and Opportunities in Cloud and Edge Computing

Description CMC Microsystems is pleased to organize the third workshop on accelerating AI, highlighting the challenges and opportunities of AI acceleration from the cloud to the edge. This workshop aims to bring together experts from industry and academia to share their latest achievements and innovations in the field of AI and machine learning algorithms, software,

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QSciTech-QuantumBC Virtual Workshop 2022: Quantum Machine Learning with Gate-Based Quantum Computing Using IBM Quantum

Quantum computing has the potential to solve problems beyond the capabilities of conventional supercomputers, and could revolutionize the advancement of several fields, including materials science, biochemistry, finance, logistics, and artificial intelligence. It is thus essential to develop concrete expertise to take advantage of the new possibilities that will arise from quantum computing.  In 2020, the

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Xilinx Versal AI Core Series VCK190 Evaluation Kit

What’s Included Xilinx VCK190 Evaluation Board QSPI Book Module Pmod Module 2x Ethernet Cables 2x Micro SD cards 180W (12V) power supply Resources Quick Start Guide, Targeted Reference Designs, PetaLinux Board Support Package and more are available at the Xilinx VCK190 Product Webpage System Controller Image & Beam Tool Applications The VCK190 Evaluation Kit is

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BARVINN: A Barrel RISC-V Neural Network Accelerator

Features Complete design and verification environment Access to the FPGA based emulation Easy integration with TensorFlow and Pytorch Applications Low power AI at the edge Hardware Software exploration Machine learning accelerator on FPGA Presentation Accelerating AI 2021 – Challenges and Opportunities in Cloud and Edge Computing Resources BARVINN Source Code BARVINN: Barrel RISC-V Neural Network

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Atlas 800 Training Server

AI-oriented heterogeneous computing architecture provides hierarchical APIs to help you quickly build AI applications and services based on the Ascend platform. Features The ultimate computing density 2.56 PFLOPS FP16 in a 4U space 1.7x the computing density of industry peers Superior perf./watt Supports air cooling and liquid cooling 2.56 PFLOPS/5.6 kW1 ultra-high energy efficiency, 1.3x

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Atlas 200 DK AI Developer Kit

AI-oriented heterogeneous computing architecture provides hierarchical APIs to help you quickly build AI applications and services based on the Ascend platform. Features High integration Powered by the Huawei Ascend 310 AI processor, and integrates various peripheral interfaces and the Mind Studio, facilitating access to the development environment and enabling quick development Easy-to-use software environment Mind

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thinkRF R5500-427 27GHz Real Time Spectrum Analyzer

System Overview Sampling at 125 MS/s with a selectable IBW up to 100MHz, the R5500 RTSA performs with excellent dynamic range, phase noise performance and speed. The CMC system is comprised of the R5500 RTSA, test antennas and a laptop containing the thinkRF application & integration software in a portable hard-shell carrying case. Keysight’s 89601C

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COMSOL Multiphysics Intensive Online Training Course

This course is the recommended starting point for learning how to use the COMSOL Multiphysics software. During this training course, you will develop a strong foundation for your future Multiphysics modeling work. It will be started at an introductory level, leading students through the essential steps needed in all analyses (geometry creation, interactive meshing techniques, model setup, postprocessing, etc.) Then, it will move into more advanced topics, such as

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Using Cluster Sweep Node and Batch Mode License in COMSOL Multiphysics Simulation

This document explains how to optimize the parallelization of parametric computations of COMSOL Multiphysics by using Cluster Sweep node and Batch mode license, which is available for all COMSOL licenses provided by CMC. Note: This procedure is based on GUI access to COMSOL using the CMC cloud infrastructure and is not currently available using command

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Calibre Manufacturing Tools in the NDN (RET, MDP and FRACTURE tools)

Siemens’ Calibre CAD suite incorporates a number of diverse tools for mitigating and predicting manufacturing imperfections generated during the fabrication of optical and electronic components. This overview page is meant to give a brief introduction to the stages through which each design must pass from circuit schematic to finished, physical semiconductor chip, and the roles

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Synopsys TCAD Sentaurus Training Modules on the CMC STC Disk

We have received a number of requests to provide training and examples for the TCAD Sentaurus CAD suite. The table below lists most of the introductory training modules for this suite. They are designed specifically for new users, and provide work-able examples and exercises. Not all modules are listed here. For the complete list, and to run

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Uploading a Simulation File to the CAD Compute Cluster

The main webpage for CMC’s CAD Compute Cluster is here: https://www.cmc.ca/cad-compute-cluster/. Step-by-step instructions for logging into and using the Cluster are outlined in Getting Started with CMC CAD Compute Cluster. CMC recommends using a secure file transfer (SFTP) client to transfer files to and download them from the Cluster. In this document, we describe two

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Initialising the CAD Compute Cluster for the First Time

Using Secure Socket Handler (SSH) in the CAD Compute Cluster Secure Socket Handler (SSH) is a form of security granted to users in this cluster. A passcode is generated by a small script, and placed on each node (login, compute) to permit intra-cluster/inter-nodal communication during a user’s simulation runs. Figure 1: The Nodes in the CAD

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Load Share Facility (LSF) Job Scheduler: Commands to set up your Environment

Module Commands in an LSF 10.1 Environment Note: In the following descriptions, the symbols “$” is used to indicate a LINUX terminal command prompt. The LSF Job Scheduler in the CAD Compute Cluster runs constantly, and never has to be started. It has been configured with certain queues that handle requests for cores and memory.

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Using CMC Cloud Design Environment – Windows

Table of Contents Introduction CMC cloud design environments are virtual on-demand secure design environments. These environments include CAD tool suites and can host Process Design Kits (PDKs). This document guide you to use CMC cloud where you can perform your research. Accessing CMC cloud Access to CMC cloud is included with many of the CAD Tools available

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Teledyne Micralyne Micralyne MicraGEM-Si™ MEMS Process

Micralyne MicraGEM-SiTM is a silicon-on-insulator (SOI) based MEMS process which will reduce the initial cost and risk of prototype development, while speeding the time to market for MEMS- Based devices. MicraGEM-SiTM is ideally suited for the manufacture of tilting mirrors and mirror arrays for variable optical attenuators (VOA) and wavelength selective switch (WSS) modules, commonly used in

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AMF Silicon Photonics General-Purpose Fabrication Process

Silicon-on-insulator, 220-nm top Si film, 3000-nm buried oxide (BOX) High resistivity handle wafer (>750 ohm-cm) 193-nm deep UV lithography for waveguides, enabling features down to approximately 140 nm Two partial etches and one full etch of the top silicon PECVD Silicon Nitride waveguide integration 6 implants for optical modulators (P++, P+, P, N++, N+, N) Germanium

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AMS 0.35 µm CMOS Process Technology (High-Voltage)

This 0.35 µm CMOS technology offers four metal layers, digital standard cells, an anti-reflective coating and high-efficiency photodiodes, and bulk micromachining. CMC’s multi-project wafer service delivers this technology from austriamicrosystems, offering three processes: Basic, Opto and High-Voltage (see details below). The technology is suitable for: High-Voltage Process (H35B4D3) Details Technology Features: 4 metal and 2 poly layers with a

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AMS 0.35 µm CMOS Process Technology (Opto)

This 0.35 μm CMOS technology offers four metal layers, digital standard cells, an anti-reflective coating and high-efficiency photodiodes, and bulk micromachining. CMC’s multi-project wafer service delivers this technology from austriamicrosystems, offering three processes: Basic, Opto (see details below) and High-Voltage. Opto Process (C35B4O1) Details Technology Features: 4 metal and 2 poly layers (similar to basic option) High-efficiency

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AMS 0.35 µm CMOS Process Technology (Basic)

This 0.35 μm CMOS technology offers four metal layers, digital standard cells, an anti-reflective coating and high-efficiency photodiodes, and bulk micromachining. CMC’s multi-project wafer service delivers this technology from austriamicrosystems, offering three processes: Basic (see details below), Opto and High-Voltage. Basic Process (C35B4C3) Details Technology Features: 4 metal and 2 poly layers Supply Voltage: 3.3/5V Bulk-micromachining option, allowing

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TSMC 0.35 µm CMOS Process Technology

This 0.35 μm CMOS technology is available through CMC’s multi-project wafer service, which delivers Taiwan Semiconductor Manufacturing Company (TSMC) nanometer and micron-scale CMOS technologies. Applications The 0.35 µm CMOS (CMC term is CMOSP35) process is suitable for: Analog circuits RF circuits Mixed-signal circuits Process Details Electrical Contact Forming Technology: Polycide Layers: 4 metal, 2 poly Supply Voltages:

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Synopsys Design Tools

Synopsys provides a comprehensive portfolio of tools for silicon design and verification, FPGA development, photonic device and system design, fabrication process and atomic-scale modelling. Software tools available in this bundle include: Custom Design Digital Design Silicon Lifecycle Management Verification Optical Design Photonic Design Silicon Engineering For more information, see the Synopsys Electronic Design University Program. Licensing

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