The LTCC A6M Shared Run is a standardized MPW-style prototyping option for ceramic circuits and substrates built on Ferro A6M material. It combines a fixed stack-up with an available PDK, L-Edit layer definitions, and fast/slow DRC rule sets to support manufacturable submissions. The LTCC@ETS platform offers an LTCC A6M Shared Run for multi-layer ceramic prototyping based on […]
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CMC offers this process as part of a Multi-project wafer (MPW) service. This process consists of Aluminum-Aluminum oxide-Aluminum Manhattan-style Josephson junctions with an additional Nb layer for the other circuit structures. The substrate is sapphire, and the critical current density is 2 uA/um2 with a junction size ranging from 100 nm to 300 nm. Note:Â The
3iT Superconducting Quantum Al_JJ_Nb Two-layer Process Read More »
CMC Microsystems offers access to the GlobalFoundries® 55 nm BCDLite (GF55BCDLite) technology, designed for applications requiring Bipolar-CMOS-DMOS (BCD) technology, such as high-performance Power Management ICs (PMICs). This process provides optimized RDS(on) for efficient power delivery and features low-power and high-voltage LDMOS transistors, making it ideal for power-sensitive designs. CMC Microsystems offers access to this technology
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CMC Microsystems offers access to the GlobalFoundries® 28 nm Super Low Power Extended (28SLPe) technology, an ideal process for energy-efficient, mixed-signal, and RF SoC applications. The 28SLPe technology provides best-in-class power efficiency for a wide range of applications. Its optimized 28 nm planar transistor technology enables ultra-low leakage and supports high-density designs for performance and
GlobalFoundries® 28 SLPe Read More »
This process allows for fabrication of coplanar structures on a high-resistivity silicon substrate, like resonators with quality factors of about one million. Aluminum junctions patterned by electron beam lithography can be added on top to make complete qubits CMC offers this process as part of a multi-project wafer (MPW) service. Al-ALOx-Al junctions in a range
VTT Aluminum Junction Process Read More »
The GlobalFoundries® (GF) silicon photonics (SiPh) foundry portfolio is designed to help you deliver more data faster, farther, and more efficiently than traditional CMOS technologies. 45SPCLO, built on a 45 nm SOI platform, enables monolithic integration of RF, analog and Si-Photonic circuits with high efficiency and high data speed. CMC Microsystems offers access to GlobalFoundries technologies
GlobalFoundries® Silicon Photonics - GF Fotonix™ (45SPCLO) Read More »
This two-layer process allows for the fabrication of Niobium side-wall passivated junctions via an Nb-Al-AlOx-Nb tri-layer, alongside an Nb wiring layer on top. CMC offers this process as part of a multi-project wafer (MPW) service. Nb-Al-ALOx-Nb trilayer junctions High-resistivity silicon substrate Nb wiring layer on top The process provides 20 copies of the designs. Applications
VTT Niobium SWAPS Junction Process Read More »
Silicon nitride with device layer thickness 400 nm and buffer oxide Layer thickness 4.5 µm 100 keV electron-beam lithography system enabling features down to 120 nm Fully etched devices (etched down to the buffer oxide) are created using an e-beam mask material and anisotropic ICP-RIE etching process. Tri-layer TiW/Al metallization and TiW alloy heater are available
Applied Nanotools (ANT) Silicon Nitride (SiN) Fabrication Process Read More »
Silicon-on-insulator, 220-nm top Si film, 2000-nm buried oxide (BOX) 100 keV electron-beam lithography system enabling features down to 60 nm One full etch of the top silicon for standard MPW run, partial silicon etching will be available in near future Tri-layer TiW/Al metallization and TiW alloy heater are available Metal oxide window, deep trench for
Applied Nanotools (ANT) NanoSOI Fabrication Process Read More »
CMC offers access to the GlobalFoundries® 12 nm FinFET technology. The 12LP technology is targeted for high-performance, power-efficient SoC applications in demanding, high-volume applications. 3D FinFET transistor technology provides best-in-class performance and power with significant cost advantages from 12nm area scaling. FinFET benefits include high drive current and soft error rate reduction vs planar technology. FinFET
GlobalFoundries® 12 LP Read More »
CMC supports prototyping services to grow a variety of structures on InP, GaAs and Ge substrates through industrial standard foundries, for research and applications in optoelectronics and photonics. Subsidized rates are available for CMC subscribers. Methods of Epitaxy Molecular Beam Epitaxy (MBE) on GaAs and Ge substrates Gas-Source MBE on InP substrate Metal-Organic Chemical Vapor
Compound Semiconductor Epitaxy Read More »
CMC Microsystems offers access to the GlobalFoundries® (GF) 22FDX™ 22 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) process technology platform for low power embedded applications. The 22 nm FD-SOI transistor technology delivers FinFET-like performance with energy-efficiency. The simultaneous high Ft /high Fmax, high self-gain and high current efficiency of 22FDX enables ultra low power analog/RF/mmWave designs. For more information,
GlobalFoundries® 22FDX FDSOI 22 nm Read More »
CMC Microsystems offers access to the GlobalFoundries® (GF) 130 nm high-performance SiGe BiCMOS technology. This technology is well suited for the design of high-speed, low-noise mixed-signal systems. The silicon-proven solutions enable you to maximize performance, integrate extensive digital and RF functionality and exploit an economical silicon platform. An advanced copper metallization feature enables higher current
GlobalFoundries® SiGe 8XP BiCMOS 130 nm Read More »
CMC offers access to the GlobalFoundries® (GF) 45 nm RF Silicon on Insulator (SOI) CMOS technology. The GF 45RFSOI technology is targeted for high performance, next-generation mobile communication infrastructure. This technology offers collective benefits of RF-centric features, device stacking, an optimized BEOL and a high-resistivity substrate. The RF centric process enhancements of 45RFSOI build on
GlobalFoundries® 45 nm RFSOI Read More »
CMC Microsystems offers access to the GlobalFoundries® (GF) 90 nm High-performance SiGe BiCMOS technology. The GF 90 nm high-performance BiCMOS technology is well suited for the design of high-speed logic/mixed-signal systems. The process is configured for 1.2 V/1.8 V/2.5 V/3.3 V high-performance operation at RF frequencies. The technology offers low noise figure, high gain and
GlobalFoundries® 90 nm BiCMOS SiGe 9HP Read More »
The GlobalFoundries® (GF) silicon photonics (SiPh) foundry portfolio is designed to help you deliver more data faster, farther and more efficiently than traditional CMOS technologies. 9WG is an industry-first SiPh foundry solution. Built on a 90 nm SOI platform, the offering enables you to leverage high-volume manufacturing along with advanced processing and controls that utilize
GlobalFoundries® Silicon Photonics 9WG Read More »
In partnership with Science Foundry, CMC offers users access to the Poly MEMS technology. Poly MEMS technology is a triple polysilicon, single metal surface micromachining process with deposited oxide (PSG) as the sacrificial material, and silicon nitride for electrical isolation from the substrate. Post-processing for Poly MEMS offers optional HF release and supercritical carbon dioxide
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Piezo MEMS is a piezoelectric-based MEMS process for ME, ECE and biomedical researchers to develop sensors, energy harvesters, ultrasonic transducers, microphones, and self-contained microsystems for automotive, aerospace, healthcare and entertainment electronics markets. Note: The expected number of chips to be delivered for this technology is 15.
Science Foundry Piezo MEMS Process Technology Read More »
CMC’s multi-project wafer service delivers the MEMS technology, through a partnership with Science Foundry. The Poly MEMS technology is a triple polysilicon, single metal surface micromachining process with deposited oxide (PSG) as the sacrificial material, and silicon nitride for electrical isolation from the substrate. CMC also offers optional HF release and supercritical carbon dioxide drying.
Science Foundry Poly MEMS Multi-User MEMS Process Technology Read More »
Micralyne MicraGEM-SiTM is a silicon-on-insulator (SOI) based MEMS process which will reduce the initial cost and risk of prototype development, while speeding the time to market for MEMS- Based devices. MicraGEM-SiTM is ideally suited for the manufacture of tilting mirrors and mirror arrays for variable optical attenuators (VOA) and wavelength selective switch (WSS) modules, commonly used in
Teledyne Micralyne Micralyne MicraGEM-Si™ MEMS Process Read More »
Silicon-on-insulator, 220-nm top Si film, 3000-nm buried oxide (BOX) High resistivity handle wafer (>750 ohm-cm) 193-nm deep UV lithography for waveguides, enabling features down to approximately 140 nm Two partial etches and one full etch of the top silicon PECVD Silicon Nitride waveguide integration 6 implants for optical modulators (P++, P+, P, N++, N+, N) Germanium
AMF Silicon Photonics General-Purpose Fabrication Process Read More »
This 0.35 µm CMOS technology offers four metal layers, digital standard cells, an anti-reflective coating and high-efficiency photodiodes, and bulk micromachining. CMC’s multi-project wafer service delivers this technology from austriamicrosystems, offering three processes: Basic, Opto and High-Voltage (see details below). The technology is suitable for: High-Voltage Process (H35B4D3) Details Technology Features: 4 metal and 2 poly layers with a
AMS 0.35 µm CMOS Process Technology (High-Voltage) Read More »
This 0.35 μm CMOS technology offers four metal layers, digital standard cells, an anti-reflective coating and high-efficiency photodiodes, and bulk micromachining. CMC’s multi-project wafer service delivers this technology from austriamicrosystems, offering three processes: Basic, Opto (see details below) and High-Voltage. Opto Process (C35B4O1) Details Technology Features: 4 metal and 2 poly layers (similar to basic option) High-efficiency
AMS 0.35 µm CMOS Process Technology (Opto) Read More »
This 0.35 μm CMOS technology offers four metal layers, digital standard cells, an anti-reflective coating and high-efficiency photodiodes, and bulk micromachining. CMC’s multi-project wafer service delivers this technology from austriamicrosystems, offering three processes: Basic (see details below), Opto and High-Voltage. Basic Process (C35B4C3) Details Technology Features: 4 metal and 2 poly layers Supply Voltage: 3.3/5V Bulk-micromachining option, allowing
AMS 0.35 µm CMOS Process Technology (Basic) Read More »
This 0.35 μm CMOS technology is available through CMC’s multi-project wafer service, which delivers Taiwan Semiconductor Manufacturing Company (TSMC) nanometer and micron-scale CMOS technologies. Applications The 0.35 µm CMOS (CMC term is CMOSP35) process is suitable for: Analog circuits RF circuits Mixed-signal circuits Process Details Electrical Contact Forming Technology: Polycide Layers: 4 metal, 2 poly Supply Voltages:
TSMC 0.35 µm CMOS Process Technology Read More »
CMC’s multi-project wafer service is offering the TSMC(CR013G) RF Mixed-Signal technology. This technology has potential applications in RF and mixed-signal systems, and is suitable for: RF and Mixed-signal designs High-speed digital circuits The CR013G PDK is available on CMC’s STC. If you do not have STC access, or require TSMC libraries, please contact [email protected]. For more
TSMC 0.13 µm CMOS RF Mixed-Signal Process Read More »
The latest product information can be found at: http://mycmp.fr/datasheet/ic-28nm-cmos28fdsoi. To start the 28-nm licensing process, please submit your design kit request to CMP directly through the link: https://mycmp.fr/requests/design-kit-141.html. Notes: STMicroelectronics prohibits use of this 28-nm technology for any medical or military applications. The expected number of chips to be delivered for this technology is 30.
STM 28nm FD SOI CMOS Read More »
ESP is a signal conditioning platform for converting trapped charges into a voltage signal. Charges are trapped on the surface by a functional material applied by the user, such as graphene, biomolecules, or quantum dots. The platform is useful for the implementation of solid-state high-performance detectors. Note:Â The expected number of chips to be delivered for
3iT Electronic Sensor Platform (ESP) Read More »
